Tools enable quick and hassle-free development of Luminary Micro’s Stellaris MCUs in a wide range of embedded control applications, yielding ultra-dense code footprints.
IAR Systems has announced the first independent development tools supporting Luminary Micro’s Stellaris family of microcontrollers. The Stellaris family features the ARM Cortex-M3 microcontroller core. When used in combination with Stellaris microcontrollers, IAR Embedded Workbench for ARM and Cortex-M3 will enable quick and hassle-free development of a wide range of embedded control applications, yielding ultra-dense code footprints.

The new tool is the latest in the IAR Embedded Workbench family, which has been providing users with advanced optimisation and intelligent linking for over 20 years.

IAR Embedded Workbench is a set of development tools for building and debugging embedded system applications using assembler, C and C++.

It provides a completely integrated development environment that includes a project manager, editor, build tools and the versatile IAR C-Spy debugger.

The new IAR Embedded Workbench for ARM and Cortex will contain a completely new highly optimising Thumb 2 C/C++ compiler.

IAR Systems’ J-Link JTAG-to-USB hardware debug probe, with industry-leading flash download speed, will be included in Luminary Micro’s Stellaris development kits.

As well as developing the technology, IAR Systems provides comprehensive technical and programming support.

‘IAR Systems is a clear market leader in providing development tools for embedded systems’, said Jean Anne Booth, Chief Marketing Officer of Luminary Micro.

‘The IAR Embedded Workbench with IAR J-Link support has been a popular tools solution for embedded systems developers for years’.

‘Now the many users of IAR Embedded Workbench that were previously limited by cost to 8 and 16bit microcontroller solutions can find a familiar tools environment on the powerful yet cost-effective Stellaris family of microcontrollers’.

‘ARM represents the largest and fastest growing segment of our software development tools business, and we believe that the price-performance ratio of the Cortex-M3 architecture is compellingly attractive to engineers’, said IAR Systems’ Chief Executive Officer Olle Eriksson.

‘We are pleased to be a leader in support of Luminary Micro’s Stellaris family of microcontrollers’.

The new development tool will be included free of charge in Luminary Micro’s Stellaris development kits, and full versions will also be available from IAR Systems.

A beta version of the compiler will be available April 2006 to selected partners, followed by a full public release in May 2006.

An evaluation version of the IAR Embedded Workbench for Cortex-M3 as well as an 8Kbyte code size limited KickStart version will be available for download from the IAR Systems website on first public release.

ARM’s RealView microcontroller development kit provides full support for the new Luminary Micro Stellaris family of microcontrollers.
ARM’s RealView microcontroller development kit provides full support for the new Luminary Micro Stellaris family of microcontrollers. The Luminary Micro Stellaris family is the first family of microcontrollers to be based on the ARM Cortex-M3 32bit processor, which is optimised for cost-sensitive applications. The RealView microcontroller development kit, launched in January, integrates the ARM RealView compilation tools with the Keil uVision3 development environment.

The RealView compilation tools enable Stellaris users to easily achieve higher performance and code density, which in turn enables them to reduce system cost.

The RealView microcontroller development kit offers an extensive range of features and benefits specifically tailored for microcontroller users, including complete device simulation and software trace, and features the easy-to-use uVision interface familiar to users of the Keil tools for 8051- and 166-based standard products.

This makes the Stellaris family of microcontrollers optimal for customers planning to migrate from 8 and 16bit applications to 32bit applications.

The ARM/Luminary collaboration on Stellaris represents an end-to-end engagement.

Luminary selected the Cortex-M3 processor as the basis for the microcontroller, then used the ARM RealView development suite and RealView ICE solution to develop and validate the design.

Then lead Luminary customers used the RealView tools to evaluate the microcontroller; these customers can now use the RealView microcontroller development kit to develop optimised applications.

‘For Luminary’s customers, our partnership with ARM provides two major benefits’, said Luminary Founder and Chief Marketing Officer Jean Anne Booth.

‘Customers can take advantage of the performance and features of the Cortex-M3 32bit microcontroller at an excellent build cost, and the RealView microcontroller development kit gives our customers a tightly coupled application development environment’.

‘ARM’s partnership with Luminary demonstrates how use of a leading-edge toolchain creates value for ARM Partners and their customers’, said Brian McAllister, Director of Marketing, Development Systems, ARM.

‘It also highlights the value of our Cortex-M3 processor’.

‘The low power, low cost ARM processor architecture has for some years been the processor of choice for embedded microcontroller applications’.

‘The Cortex-M3 processor is the smallest, lowest-power ARM processor but achieves outstanding performance for cost-sensitive applications’.

The ARM RealView microcontroller development kit is available now via Keil and ARM distribution channels.

Simulation models for StarCore’s SC1000 and SC2000 family of processors and associated peripherals are fully interoperable with the ARM RealView SoC Designer ESL toolset.]
ARM has collaborated with StarCore to create simulation models for StarCore’s SC1000 and SC2000 family of processors and associated peripherals that are fully interoperable with the ARM RealView SoC Designer ESL toolset. These processor and peripheral models are now offered in the RealView StarCore Model Library. ARM offers RealView Model Libraries, which incorporate MaxLib technology, for ARM processors and subsystem components, as well as IP models from StarCore, CEVA, LSI Logic and MIPS.

These models are used with the RealView SoC Designer for architectural exploration and system simulation to create and exercise virtual platforms.

System and hardware architects use SoC Designer’s cycle accurate and on-the-fly debugging and profiling capabilities to quickly and accurately pinpoint the optimum architecture, especially of heterogeneous multicore designs.

ARM and StarCore used the RealView ESL API transaction-level model interfaces to ensure the StarCore models achieved the highest level of interoperability with the RealView tools.

The RealView ESL APIs are the industry’s first comprehensive and openly available family of IP model interfaces for plug-and-play SystemC simulation that includes advanced model debug and profiling features.

‘The integration of the StarCore models into ARM’s RealView ESL development environment provides silicon designers with a seamless solution for StarCore system development’, said Alex Bedarida, General Manager, StarCore.

‘Having the SC1000 and SC2000 processor and subsystem family models available for use with SoC Designer gives our customers a significant competitive advantage, both in product quality and time to market’.

‘As customer design efforts focus more on systems combining IP from multiple vendors, ARM will continue to deliver best-in-class ESL design tools that make those designs commercially viable’, said Bryn Parry, General Manager, Development Systems, ARM.

‘This collaboration with StarCore demonstrates ARM’s commitment to providing the best ARM and StarCore technologies to our customers’.

New translators enable migration of Protel, P-CAD and OrCAD designs and libraries to PADS PCB design solutions.
Mentor Graphics has released new translators that enable migration of Protel, P-CAD and OrCAD designs and libraries to PADS PCB design solutions. The release of the translators makes it even easier for companies to switch over to PADS, bringing over all current libraries, databases and other existing legacy data through the push of a button. Designers wanting to take advantage of PADS superior depth of functionality, routing, ease of use and deployment can now do so with minimal effort, loss of data or time.

‘We were looking to standardise our design flow to reduce the amount of time we spent recreating parts that would work with one design tool but not another’, said Dave Wolf, Electrical Engineering Supervisor at Haas Automation, the largest machine tool builder in the USA.

‘We had concerns about losing all of our previous designs and libraries’.

‘However, after evaluating several vendors, we discovered that with PADS, we were able to get done what we needed to do quickly and cleanly’.

‘When the PADS reseller showed us how the new translators could bring over our Protel and OrCAD designs and data, PADS became the obvious solution’, added Wolf.

PCB designers and engineers are no longer trapped using older, legacy tools due to the lack of bandwidth and associate costs available to recreate their libraries.

The PADS advantages of ease of use, performance and price, combined with the new PADS translators, mitigate risk and significantly improve a user’s ROI.

These translators reduce the cost of migration by virtually eliminating the need to recreate prior design data and libraries.

This allows designers and engineers to take advantage of PADS extensive schematic design, powerful layout, interactive and automatic routing, as well as design for test and design for fabrication capabilities, all without leaving behind the intellectual property they have spent years building up.

‘Mentor Graphics continues to experience a growing number of companies switching to PADS from other PCB solutions’, said Dan Boncella, Director of Marketing for Systems Design Division, Mentor Graphics.

‘These translators are making it easier and more reliable to transition library and design data into the PADS flow, while significantly lowering the risk and providing a much faster return on investment’.

‘Mentor will continue to develop additional translators and updates to make switching to PADS a seamless and easy process’.

The new translators are available immediately and at no cost.

A specialist routing interface tool handles microstrip routing for radio frequency design within Cadstar environments.
Zuken and Finland-based Inca Systems have launched a specialist routing interface tool, iMstrip, for handling microstrip routing for radio frequency (RF) design within Cadstar environments. This new product interfaces between Cadstar, and Aplac and Agilent microstrip routing tools, allowing designers to simulate high-frequency conductor geometries in RF printed circuit boards (PCBs). Without it, the task would usually take hours in redrawing the schematic by hand to perform simulation and verification checks for RF.

With iMstrip, this task now takes only a matter of minutes.

As the schematic and PCB layout will contain both component and route shape symbols, specialised RF simulation is required.

In these designs, conductors or routes/tracks, act as components and need to be created as integral parts of the circuit.

The layout has a direct impact on the way a board works; route length and width, physical component positioning and size, and the composition of substrate material, all affect the frequency of a wave.

Accurate tuning and physical simulation of PCB conductors is critical.

It is essential to verify that the schematic that has been transferred to physical layout exactly matches what was intended by the designer.

Faults in this part of the design process not only cause circuitry problems but will also affect the core functionality.

Once the microstrip simulation routing tools have performed checks on a Cadstar design, the results can then be transferred back to Cadstar schematics for corrective design modifications using the iMstrip.

With the growth in mobile technology, harnessing the power of radio frequencies is calling for more and more designers to adopt the use of tools of this kind.

Verific Design Automation has licensed its HDL Component Software to ProDesign, a leading supplier of high-speed ASIC and SoC verification platforms.
Verific Design Automation has licensed its HDL Component Software to ProDesign, a leading supplier of high-speed ASIC and SoC verification platforms. ProDesign has integrated Verific’s C++ source code-based parsers, analysers and elaborators for Verilog and VHDL with its Chipit ASIC prototyping systems where Verific’s software is being used as the RTL front end. ‘Verific - our first choice when looking for a front-end development partner - offers an exceptional package that includes production-proven, quality software, along with excellent support and service’, said Gunnar Scholl, ProDesign’s Director of Marketing and Business Development.

‘With the integration of Verific’s HDL Component Software, we were able to expand the capabilities of our Chipit systems especially for the transaction-based verification’.

‘This enhanced concept opens new functionalities for pre-silicon system and software verification’.

Michiel Ligthart, Verific’s Chief Operating Officer, remarked: ‘ProDesign has a compelling story, and we’re delighted to be part of it’.

‘ASIC prototyping is a viable verification strategy, due in large measure to ProDesign’s tools’.

Zensys has added to its executive team and has revealed plans to relocate the company headquarters to the San Francisco Bay Area.
Zensys, creator of the Z-Wave wireless mesh networking technology for home control, is to relocate its company headquarters to the San Francisco Bay Area. The company has also announced enhancements to its executive leadership team. Tony Shakib has been appointed CEO and Steve Troyer has become Vice President of Marketing.

In addition, Per Nathanealson, who has served as Zensys’ CEO, has been named Chairman of the Board.

An accomplished executive with over 20 years of experience, Shakib joins Zensys after successful GM roles with leading technology companies including Centillium, AOptix and Nortel.

Troyer brings 20 years of sales and marketing experience, including senior roles with leaders like Cisco Systems, Linksys and Juniper Networks.

‘I am thrilled to welcome Tony and Steve to Zensys’, said Per Nathanealson.

‘Tony brings a wealth of experience in leading highly focused teams and an outstanding track record’.

‘Steve’s marketing expertise, particularly in the consumer networking industry, is important to Zensys as we move forward with our Z-wave Alliance partners into new markets and channels’.

‘Per and the entire Zensys team have done a terrific job in developing the industry’s leading wireless control technology, Z-wave, and successfully building the market in partnership with some of the industry’s leading companies through the Z-wave Alliance’, said Shakib.

‘Steve and I are privileged to join such an incredible team and we look forward to working with Per, Zensys, and the entire Z-wave community to help move the company and the industry to the next level’.

‘Our board is really pleased to welcome Per as our Chairman’, said Bob Richardson, who has served previously served as Chairman, and remains on the Board.

‘Per’s commitment to Zensys and success in building this market over the last 4 years has been inexhaustible’.

‘His insight will be invaluable to Zensys and the board as we continue to set our strategic course’.

The company will maintain its New Jersey office to continue to serve its growing list of customers and partners.

DesignAdvance Systems has released a new version of CircuitSpace, its award-winning user-assisted PCB component placement software.
DesignAdvance Systems has released a new version of CircuitSpace, its award-winning user-assisted PCB component placement software. CircuitSpace v1.5 furthers DesignAdvance’s commitment to boosting the productivity of PCB designers. This version expands on the tool’s established hierarchical approach to printed circuit board design through enhanced auto-clustering and replication technologies.

Additionally, it improves CircuitSpace’s ability to expedite the design process by expanding on its capabilities in the areas of template libraries, automatic bypass capacitor assignments, double-sided board placement and intelligent channel and/or port duplication.

‘Since the initial release of CircuitSpace, DesignAdvance has been working hard to overcome the long standing perception that automated component placement is difficult to use and unable to make a significant impact on the PCB design process’, said Randy Eager, DesignAdvance CEO.

‘We are seeing a real change in mind set once designers are exposed to CircuitSpace’.

‘Having seen unsuccessful attempts, I was skeptical of any company claiming to have a product that automates component placement’.

‘My opinion on the subject changed since I started using CircuitSpace’, said Mark Dills, 20-year-plus veteran of the PCB business and a Senior PCB Designer with Softeq.

‘The auto-clustering and replication features alone can save hours, days, even weeks of time off of a design cycle’.

This latest release of CircuitSpace also adds features to address the challenges associated with managing frequent board design modifications so common in today’s concurrent design processes.

CircuitSpace v1.5 guides its users through the concurrent board design by: automatically identifying changes to a board design as they arrive through successive netlist imports; producing addendum clusters for newly added parts; assessing the impact of design changes on component placement and reporting part loss or gain and part type changes; and reporting on detailed changes from current board design, to quickly adapt to the new requirements and to facilitate feedback to the hardware engineer.

‘The latest enhancements to CircuitSpace present our customers with a significant upgrade to the current ‘click-and-drag’ component placement process’, continued Eager.

‘We are especially pleased with the improvements to the concurrent board design process, which underscores our goal to deliver a product that enhances the way engineers and designers work today rather than forcing them to adopt a foreign process to get their jobs done’.

Sequans Communications has adopted key components of the Synopsys Discovery Verification Platform to establish a leading-edge chip verification process.
Sequans Communications, a fabless semiconductor company that develops end-to-end standards-based silicon for broadband wireless access, has adopted key components of the Synopsys Discovery Verification Platform to establish a leading-edge chip verification process. Sequans has standardised on the Synopsys VCS comprehensive RTL verification solution, System Studio for algorithm design and system-level verification and the Formality formal equivalence checker to ensure consistency between RTL and chip implementations. Sequans has successfully released basestation and Subscriber Station chips, compliant with the IEEE802.16-2004 standard.

Both chips were developed in record time, and Synopsys’ tools helped minimise risks and delays.

Sequans plans to release its chips for the mobile WiMAX/WiBro market and is using Synopsys tools to help ensure the best time to market schedule.

‘We selected Synopsys for our verification needs because they provide a complete solution from algorithm design to implementation’, said Bertrand Debray, Sequans Vice-President of Engineering.

‘It is important to us that an electronic system-level (ESL) tool for algorithm design and analysis be linked closely with the RTL verification process’.

‘Synopsys provides this connection with its well-integrated combination of System Studio and the VCS solutions’.

‘In addition, the Formality formal equivalency checking process ensures that our RTL is consistent with our final ASIC implementations’.

‘Synopsys’ Discovery Verification Platform is the industry’s leading system, RTL and gate-level verification solution’.

‘The VCS solution’s integrated high-performance testbench-based verification environment is ideal for verifying complex chips in the rapidly growing WiMAX space’, said George Zafiropoulos, Vice President of Marketing, Verification Group, Synopsys: ‘This integration, when combined with our Reference Verification Methodology (RVM), yields a complete, high-performance process for verifying the industry’s largest and most complex chips’.

STARC has adopted IC Compiler, Synopsys’ next-generation place-and-route solution, in its newly released STARCAD-21 V3.0 production flow.
The semiconductor technology Academic Research Centre (STARC) has adopted IC Compiler, Synopsys’ next-generation place-and-route solution, in its newly released STARCAD-21 V3.0 production flow. STARC is an influential consortium of Japan’s major semiconductor manufacturers that is seen as leading the way on advanced design methodologies in Japan. It provides its members with a comprehensive RTL-to-GDSII design methodology called STARCAD-21 that incorporates the latest tools, libraries, and flows for 90nm and below system-on-chip (SoC) design.

STARC’s goals for this release of STARCAD-21 were to reduce design margins and to improve the efficiency of the RTL-to-GDSII flow.

STARC incorporated IC Compiler into the STARCAD-21 flow because it provides up to 2X faster run times and better quality of results (QoR) compared with the previous-generation STARCAD-21 flow.

‘Synopsys had very impressive projections when they first introduced us to IC Compiler’, said Nobuyuki Nishiguchi, Vice President of the Design Methodology Group at STARC.

‘We are happy to confirm that IC Compiler has indeed delivered 2x faster run times, better QoR, and smaller area for high-performance designs’.

‘This new release of STARCAD-21 with support for IC Compiler represents a big step forward for our member companies in achieving high designer productivity’.

STARC has invested months of intensive effort to build the new STARCAD-21 flow and to thoroughly evaluate all its elements.

It delivered to its 11 members a flow with increased designer productivity that also supports a range of advanced capabilities in test, hierarchy, clock planning and low-power design.

To achieve these goals, STARC adopted not only IC Compiler, but also DFT MAX for test compression and Synopsys’ new high-accuracy CCS library format.

CCS library models allowed STARC to reduce the design margin for on-chip variation by 5% and boosted productivity by providing a 50x speed-up in the development of noise libraries.

IC Compiler’s unique extended physical synthesis (XPS) technology enables the STARCAD-21 flow to efficiently deal with increasingly common multi-mode designs.

IC Compiler’s concurrent multi-mode capability was the key to significant improvements in performance and turnaround time.

For example, a RISC core with six operating modes and two process corners was concurrently optimised across all modes by IC Compiler.

Thanks to XPS’ true concurrent optimisation for timing and area, there was a 5x improvement in turnaround time for post-detail routing optimisation.

Further efficiency gains were measured in STARCAD-21 resulting from the excellent correlation of IC Compiler to PrimeTime SI signoff timing and the simplified Tcl scripting.

‘We are already seeing very strong momentum with IC Compiler in Japan’, said Antun Domic, Senior Vice President and General Manager of Synopsys’ Implementation Group.

‘As major Japanese design houses are closely following developments at STARC, STARCAD-21 V3.0 featuring IC Compiler is an added boost’.

‘We look forward to working closely with customers to help them realise the productivity gains validated by STARC’.