Development kit challenges Japanese SoC designers
Categories: Design and Development HardwareThe Toshiba MeP Development Kit has been chosen as the design platform and environment for a nationwide digital media SoC design challenge.
Celoxica’s Toshiba MeP (Media Embedded Processor) Development Kit has been chosen as the design platform and environment for a nationwide digital media SoC design challenge. This announcement is the dividend of years of collaboration and investment made by Celoxica, Toshiba and the Japanese VLSI Design and Education Centre (VDEC) into semiconductor solutions and system level design for very complex system-on-chip (SoC) design. Selected by the VLSI Design and Education Centre (VDEC), the central hub of Japanese university expertise for VLSI technology, research, teaching and development, Celoxica’s technology was chosen as the most fit-for-purpose and usable solution.
It will be used by teams of specialist SoC developers to create award winning designs around Toshiba’s MeP architecture.
Due to the levels of complexity and performance involved with such designs, the robust SoC prototyping and validation features of Celoxica’s technology were cited as key factors in VDEC’s decision.
Celoxica’s Toshiba MeP Development Kit provides a comprehensive package of ESL design tools, programmable hardware platforms and utilities to help designers develop high performance SoC designs.
As well as offering MeP processor IP, the kit is fully integrated into Toshiba’s MeP design flow to enable the rapid creation and validation of complex designs from algorithmic models.
Supplied with the Kit is Celoxica’s award winning DK Design Suite of system design tools, video IP and application programming interfaces (APIs).
‘VDEC has been pleased with the use of Celoxica design tools and boards for many years’, said Dr Kunihiro Asada, Director of VDEC.
‘We now need to embrace and meet the challenges of ever more complex semiconductor design and need a configurable platform solution to do this’.
‘Our selection of solutions from Celoxica and Toshiba will help meet the needs of future SoC design education’.
Toshiba’s configurable processor MeP core has already been deployed into mass volume products such as DVD players, intelligent vehicles and other very high performance image processing systems.
Its inherent configurability reduces turn around and delivers architectures optimised to the application or customer specification.
Toshiba will sponsor a prise for the winning design and it is anticipated that the design will be taken through to silicon fabrication.
‘It is an honour to be selected as the technology platform provider for such a prestigious and demanding design challenge’, said Dr Stephen Chappell, General Manager and Representative Director of Celoxica Japan.
‘This decision reflects not only on the investment we have made into our technology, but also the relationships with corporations and organisations at the forefront of advanced electronics design’.
After completion of the design challenge VDEC expects to roll out the platform solution to over 150 Japanese universities and 640 research groups who are part of the VDEC network.