MediaTek has adopted the Mentor Graphics Eldo simulation tool as its standard Spice simulator for memory characterisation.
MediaTek has adopted the Mentor Graphics Eldo simulation tool as its standard Spice simulator for memory characterisation. Eldo provides the high accuracy and impressive runtimes required for memory designs, and is compatible with existing memory characterisation flows. Eldo is now one of the signoff tools at MediaTek used for memory characterisation.

‘We are extremely pleased that MediaTek has adopted Eldo as their signoff tool’, said Jue-Hsien Chern, Vice President and General Manager, Deep Submicron Division, Mentor Graphics.

‘With 0.13um and below technologies, the complexity of designs and nanometre effects impose stringent demands on the accuracy and performance of the signoff characterisation tool’.

‘The adoption of Eldo by MediaTek demonstrates a superior technology for nanometre designs’.

Eldo is the simulator chosen by IC silicon vendors and fabless design centres.

Worldwide designers use Eldo on designs from the lowest complexity of a single cell to a system consisting of several hundred thousand transistors.

Eldo speeds up the design and verification of complex analogue/mixed-signal circuits.

Semiconductor Manufacturing International Corporation (SMIC) has adopted Mentor’s Eldo simulation tool as an internal Spice simulator for analogue circuits.
Semiconductor Manufacturing International Corporation (SMIC) has adopted Mentor’s Eldo simulation tool as an internal Spice simulator for analogue circuits. SMIC fully supports Mentor’s Eldo based on its proven performance and convergence capabilities. In addition to 0.18-micron, SMIC will now provide Eldo device models on SMIC’s 0.13-micron and smaller process technologies aimed at satisfying the design needs of Mentor’s and SMIC’s mutual customers.

‘SMIC conducted comprehensive evaluations of Mentor’s Eldo capabilities, and the extensive results demonstrated that it is an ideal simulation tool for our technologies’, said Paul OuYang, Vice President of Design Services at SMIC.

‘Eldo now forms part of our signoff tools for designs targeting 0.13-micron and below processes’.

‘We are extremely pleased to be working closely with SMIC and providing them with a complete simulation solution through Eldo’, said Jue-Hisen Chern, Vice President and General Manager, Deep Submicron Division, Mentor Graphics.

‘With their proven analogue design simulation capability, SMIC will continue to be at the forefront of chip designs, while Mentor’s Eldo strives to be the simulator of choice for IC silicon vendors and fabless design centres’.

System CAD (SCAD) is an entirely new method of managing all activities during system design and manufacturing processes, says Alex H Chernyak.
Design of modern electromechanical equipment has become a complex task where competitive pressures demand rapid introduction of innovative products. To be a market leader a company has to operate quickly and efficiently reducing costs and streamlining the take to market process. A primary business driver today is progressing product complexity and customisation.

Products increasingly include intricate mechanics, electronics, and software.

The most effective way to improve the product design process is to account for all component attributes and design constraints at the concept stage.

That’s why in attempt to achieve dramatic productivity increases, companies are increasingly turning to CAD tools and PLM systems.

However, the existing tools only improve specific portions of what is still considered to be a manual and highly error-prone design process - and are not designed to automate the process at a systems level.

Additionally, more than two-thirds of the typical engineering process involves routine, time-intensive tasks.

The challenges are therefore to improve the speed and effectiveness of the product development process, radically reduce the time taken to create new innovative designs, and provide significant savings across every part of the design to manufacturing cycle.

With these challenges in mind, TurboTools is the first company in the industry that offering the next generation engineering automation solution that goes beyond the capabilities of traditional EDA applications.

Bridging the gap between MCAD and ECAD tools, TurboTools’ solutions define the new market segment for EDA tools called system CAD or SCAD.

TurboTools views SCAD as an entirely new level of managing all design and manufacturing activities during the system integration.

SCAD functionality will go not only bridging the gap between mechanics and electronics, but also will manage both disciplines under one umbrella.

SCAD tools, when mature enough, should take leading role for entire design process for electromechanical equipment.

TurboTools’ flagship product, CablEquity is the first product in the SystemEquity family that will revolutionise the hardware electrical systems design process.

The solution is based on TurboTools’ patented methodology that represents the entire hardware electrical systems (HES) design, manufacturing and validation as an enlarged SoC.

CablEquity is an out-of-the-box interactive end-to-end design environment for cable and harness assemblies.

CablEquity combines the management of electrical and mechanical requirements to fully automate the product design including: import/export to and from CAD systems; components search and selection; design rules check and product validation; product lifecycle management; and automatic output of all required engineering drawings and documentation.

The idea behind CablEquity was inspired by discussions with industry leading electromechanical equipment manufacturers deeply involved into design of hardware electrical systems.

Typically, electrical harnesses are designed and released to manufacturing without optimisation of components, and frequently with design faults.

These design faults may need to be fixed or patched as a costly, secondary manufacturing process.

Also, because functional specifications of complex electromechanical systems are changed constantly, harness design has to be constantly updated to fix the problems of the previous release and to incorporate the modifications for the latest system features.

In addition, hardware electrical systems must integrate a large number of components and account for the multitude of requirements such as heat, interference, resistance, and so on.

Typically the design of electrical systems is started late in the process, and can take months to complete.

The resulting design is rarely optimal.

Analysis of the electrical design process in number of companies form different industries reveals a common list of problems that include: poorly defined development process; absence of tools or procedures for applying hierarchical design methodologies poor integration between design teams involved in design; poor integration between MCAD and ECAD tools; absence of a formal process for capturing previous knowledge; lack of procedures and processes to enforce design consistency; and prevalence of manual, tedious and time-consuming steps.

Although it may appear that the electrical design process has been significantly enhanced through the use of CAD tools, in reality these tools have been developed to automate design tasks without reference to the actual design requirements.

At no stage, however, has the process been improved to more closely match the way that designers think about the design requirements.

There are opportunities for incredible savings through usage of improved design tools and processes.

Deployment of an automated design tool, which can reliably apply best practice design procedures, offers the possibility of significant reductions in the design cycle time as well as an improved electrical system performance.

CablEquity interactive design environment, re-engineers the electrical design process so that a higher quality of design can be achieved in a much shorter period of time.

CablEquity allows engineers to capture, represent, and verify the entire electrical system working through a series of steps that capture and enforce design requirements.

The definition of a hardware electrical system requires the integration of a number of different viewpoints of the product.

For instance, the system can be seen as an assembly of a large number of simple electrical circuits, or it can be seen as a challenge to mechanical engineers as they seek to find the optimum routing of the cables in order to minimise the weight and simplify installation of the cables; or, it can be seen as an assembly of components whose cost can be optimised by proper selection of component specifications.

This is where the power of CablEquity’s pays off allowing engineers to address the full spectrum of design challenges.

First and foremost, the interactive design environment offers the ultimate flexibility for engineers allowing them to design electrical systems using either top-down or bottom-up approach.

Secondly, the reach database with parametric cross-reference search engine speeds up component selection while enforcing design rules.

And finally, the whole system can be validated at the design stage.

One of the largest limitations of the established design processes is the resistance to changing design specifications.

Growing complexity and the interconnected nature of the modern systems forces engineers to start cables and harnesses design when the specification and layout of the entire system is more or less complete.

If the designers attempt to begin the electrical design task earlier, when specifications are still changing, then they find that much of their previous work is rendered obsolete each time something changes.

For example, moving the location of the SCSI controller by some distance may appear a simple modification.

After all, the connectivity of the SCSI cables will remain the same although their individual lengths will, of course, change but here is the problem.

Changing the lengths of the SCSI cables affects the resistance of the cables and specifications for the SCSI bus.

Changing the resistance of the cables changes the voltages within the attached circuits.

Each of these circuits will have specific requirements for power and voltage at key components.

Changing the location of the SCSI controller has therefore impacted on no working condition of entire SCSI bus.

Changing the location of one component can require the redesign of interconnects or even attached circuits.

The problem is amplified because a large proportion of the cables within a complex system service more than one circuit.

Sometimes the process is so complex that in most instances the designer is unable to define directly the component and cable parameters to meet the circuit requirement.

Instead, designers have to wait for a live prototype to discover whether the resulting performance meets the requirements.

The designer then begins to tune the individual component and cable parameters until the analysis tools show that the required performance has been achieved.

The process of creating the electrical system is therefore, not surprisingly, measured in months or sometimes even in years.

Traditional software tools have provided support to individual parts of the design process but have offered little in the way of true integration.

Indeed, the task of integration has been left to the designer, who must ensure that when a change is made, each of the individual software tools used in the process is properly updated.

These traditional tools are characterised by a requirement for a large amount of time-consuming human interaction before they can complete their task.

The requirement for the designer to maintain consistency between each of the software tools provides a further opportunity for errors to be introduced.

With CablEquity, any change request can be processed and validated in a matter of minutes.

Extensive versioning and project management capabilities of the system eliminate the internal resistance to change and results in better designs.

CablEquity eliminates design errors by ensuring design correctness and completeness at each step of the design workflow.

It allows the user to work with an entire design process in terms of engineering design rules and to integrate any number of design methodologies into a single product.

To end users this means that they can move effortlessly from electrical specification to engineering drawing and documentation within a single unified experience.

The design rules, which are embedded within CablEquity’s business logic and the parametric search engine, allow complete automation of all routine design activities.

The design engineer only sets the requirements, and the system automatically generates all required documentation, which meets the design goals.

The automated process is fast, error-free, and uses a series of design optimisation strategies, which would be too time-consuming for traditional design methods to use.

A process, which has traditionally taken days or weeks, can now be completed in minutes.

Using CablEquity, companies can begin electrical system design early.

Even though accurate components requirements are not available in the early stages of design, the user can specify expected parameters and then refine the component values as more accurate information becomes available.

This iterative process is made possible by the next generation speed in design completion.

Product definition is not limited to engineering design.

It also includes information about iterative changes that are made during the product’s lifecycle.

This information must be maintained throughout product lifecycles and leveraged in future products.

That’s why CablEquity includes powerful product lifecycle management capabilities for product-centric configuration management, document management, and rapid change management.

Changes, which are made to any design, will automatically generate a new version of documentation.

This allows designers to leverage previous versions at a later time, allowing preferred design methodologies to be encapsulated and applied to future designs.

To optimise operational efficiency and minimise development costs, electronics and technology companies need to automate key business processes associated with their product lifecycle.

An integrated design environment, or SCAD, is guaranteed to accelerate product introduction, improve product margins, or integrate a complex supply chain.

Calibre OPCverify signals the beginning of a new generation of OPC technology, and expands the design for manufacturing (DFM) solutions from Mentor.
Calibre OPCverify signals the beginning of a new generation of OPC technology, and expands the design for manufacturing (DFM) solutions from Mentor. Calibre OPCverify addresses the challenge of managing the impact of ‘process variability’ on yield. Process variability can have a dramatic effect on yield.

This is especially true in the lithographic process where variability puts image fidelity at risk even when the operating conditions of the lithographic system (lithographic process window) are acceptable.

To reduce the risk of silicon failure, avoid costly respins and ensure acceptable yield, Calibre OPCverify detects lithographic errors or marginalities caused by process variability before the design goes to the mask or wafer manufacturer.

The increased complexity of resolution enhancement technology (RET) at 65nm is impacting lithographic yield in several ways.

The major contributors to declining yields are: a smaller lithographic process window, increased sensitivity to layout topology in the lithographic process, and complex mask rule constraints that impact the application of RET.

These issues must be addressed with a fast, accurate and easy to use RET verification solution that detects yield-limiting conditions.

Calibre OPCverify, which uses silicon-proven simulation models from Calibre OPCpro, is the next generation of RET verification, providing 100% simulation coverage of the entire chip to ensure silicon-patterning success.

The Calibre OPCverify pixel-based simulation engine accounts for the effects of process variability using patented algorithms that define the conditions (dose, focus) that adversely impact pattern transfer.

All Calibre OPCverify modelling capabilities have been thoroughly characterised for the most advanced process conditions in production, including immersion lithography.

The rigorous model development and verification methodology used for the Calibre OPCverify tool allows it to satisfy the stringent requirements for both RET recipe validation and mask verification.

The setup and configuration of Calibre OPCverify is enabled through a user interface called the Calibre Verification Center.

With Calibre OPCVerify and the Calibre Verification Center, a comprehensive and accurate RET mask verification flow can be integrated seamlessly into existing post-layout flows in less than 24 hours.

Another benefit of using Calibre OPCverify and the Calibre Verification Center is that the tools take advantage of existing hardware in the most optimised way possible.

With the combination of high-speed compute power available on today’s workstations, and the concurrent processing functionality in Calibre MTflex, very fast turn around times for full-chip RET verification can be achieved.

Because of the design-independent nature of the tool, users experience very predictable runtimes and excellent scalability.

While actual run time is dependent on the hardware used, the Calibre OPCverify terapixel simulator is scalable to hundreds of CPUs, and can handle flat or hierarchical data.

‘Verification of post-OPC flow output is critical to minimising costly mask respins and time-to-market delays’, said Dr Choi Byoung Il, OPC Manager, Technical Support Division, Technology Development at Chartered Semiconductor Manufacturing.

‘Augmenting our existing pattern transfer accuracy checking methods with a lithography process window verification capability enhances our ability for early identification of process-sensitive structures across the chip, thereby improving the quality of OPC’.

‘For 90nm and smaller technology nodes, the complexity of OPC and the constraints that go with it require verification to prevent silicon failures’, said Joe Sawicki, Vice President and General Manager for the Design-to-Silicon Division at Mentor Graphics.

‘Some customer sources claim that 50% of all mask respins can be avoided by simply verifying the OPC for the effects of process variability’.

‘Calibre OPCverify yields a powerful return on investment through savings in mask costs and more predictable yield’.

Calibre OPCverify and the Calibre Verification Center are available immediately.

Pricing starts at $80,000.

Two new products analyse the enormous amounts of data generated during the post-layout simulation of systems on a chip and integrated circuits.
Sandwork Design has developed two new products for analysing the enormous amounts of data generated during the post-layout simulation of systems on a chip (SoCs) and integrated circuits (ICs). The new Sandwork tools are of special interest to electronics engineers designing and verifying mixed-signal ICs who have to analyse huge sets of extracted netlists with Spice-level simulation waveform data files from industry-standard circuit simulators. Sandwork’s waveform viewing technology, coupled with universal wave format coverage, is ideal for these needs.

SX CDS-Link ENS, a new product, is integrated into the Cadence Virtuoso custom design platform for the design and verification of complex mixed-signal SoCs.

Designers of these chips need to be able to quickly view extracted simulation results to identify problems in the chip design.

For example, crosstalk and ground bounce are hard-to-diagnose problems that often go undetected during the post-layout verification process, since the randomly generated RC net names in the simulation results make it extremely difficult to find the original ideal net that is the source of the problem.

By using SX CDS-Link ENS, designers can cross-probe the simulation waveform to the original ideal schematic, quickly identify any problem nodes, and pinpoint the cause by further examining the corresponding layout area.

ChipView, now in production, is a visualisation and waveform debugging tool based on post-layout RC extracted DSPF (detailed standard parasitic format) netlists.

DSPF netlists contain randomly generated net names, making it difficult to debug the netlist itself and to correlate the simulation results.

In the past, designers have had no easy way to read these results.

ChipView gives designers an automated tool for debugging extraction problems.

With ChipView, designers can now see a topographical stick diagram that is automatically generated by the tool.

While viewing the diagram, designers can easily perform such tasks as identifying floating nets and viewing trace resistance and capacitance to see if there are missing traces, opens or shorts, and so on.

Designers can easily see automatically calculated point-to-point trace resistance, resistance gradients, and total trace capacitances for interconnect debugging.

With simulation results, ChipView can further provide waveform cross-probing to the auto layout-like stick diagram.

ChipView is the only tool on the market that automatically calculates total trace resistance from any two connected extracted nodes, and automatically summarises top-grounded and top-coupling capacitances.

Lego Mindstorms NXT includes an all-new programming environment, which is based on the NI LabView graphical development software.
National Instruments and the Lego Group have announced their collaborative development of the software component to the next generation of Lego Mindstorms robotics. Lego Mindstorms NXT includes an all-new programming environment, which is based on the NI LabView graphical development software, and is PC- and Mac-compatible. The new product, announced at the Consumer Electronics Tradeshow in Las Vegas, will be available in August 2006.

Furthering the global success of the original Lego Mindstorms Robotics Invention System, introduced in 1998, the Lego Group is taking advantage of new technologies such as a 32bit processor, new motors and sensors, Bluetooth wireless communication and enhanced software development tools.

The new software, powered by LabView, provides an intuitive yet feature-rich programming environment allowing for click-and-drag icon-based programming.

Younger users will find it much easier to create their own programs, and older users will appreciate the ability to create sophisticated programs for their robots.

The new software will be used in both the retail and educational versions of Lego Mindstorms NXT.

‘We are thrilled to collaborate with National Instruments on development of the NXT software environment’, says Soren Lund, Director of Lego Mindstorms.

‘To broaden the base of Mindstorms users among younger children and more advanced robotics designers, it is important to get the product design right, but also to provide unlimited potential through the software tool’.

‘Using the sophisticated NI LabView engine allows us to maintain everything users appreciate about the current Mindstorms experience, but then go the extra mile to provide a tool that is easy enough for a 10-year-old to master on a surface level and technical enough for an adult user to be challenged and inspired to create’.

‘NI shares our commitment to inspiring creativity and innovation in children, and, working together, we are making the next-generation product experience smarter, stronger and more intuitive than ever’.

The Lego Group and National Instruments have a long-standing relationship that began in 1998 with the development of RoboLab, the programming software used in the Lego Mindstorms for Schools product.

RoboLab software, which is also based on LabView, is available in 17 languages and has helped make Lego Mindstorms for Schools the leading robotics learning and invention system for educators worldwide.

‘Developing a version of LabView for Lego Mindstorms presents a unique opportunity for National Instruments to run LabView on a high-volume embedded platform and create a development environment that works equally well for young children, scientists and engineers’, said Ray Almgren, Vice President of Product Marketing and Academic Relations at NI.

‘Our initial collaboration with the Lego Group to develop RoboLab resulted in a very successful product for Lego Education and also drove enhancements to LabView that our customers benefit from today’.

‘This new collaboration will make a version of the LabView graphical environment available to hundreds of thousands of children worldwide on the most popular robotics invention system’.

‘We are fortunate to work with a company whose products are inspiring children to be innovative and creative and possibly pursue careers in science and engineering’.

AccelChip has announced the immediate availability of its 2006.1 version of AccelChip DSP Synthesis and AccelWare IP toolkits.
AccelChip has announced the immediate availability of its 2006.1 version of AccelChip DSP Synthesis and AccelWare IP toolkits. New in 2006.1 is M2C-Accelerator, an option to AccelChip DSP Synthesis that extends the company’s model-based design solution adding automatic generation of C++ verification models from Matlab. Prior to M2C-Accelerator, companies designing algorithms in Matlab that experienced excessive verification run times, or required system-level verification in a C environment, were required to manually convert Matlab models to C.

Now, this process is made automatic, fast and error-free with M2C-Accelerator.

Design teams are now able to develop algorithms faster and explore a range of architectural solutions in less time.

The C++ models generated by M2C-Accelerator can be used in Matlab, Simulink, Xilinx System Generator and stand-alone C verification environments.

AccelChip’s M2C-Accelerator customers working on algorithms for applications such as 802.11 and global positioning satellites (GPS) have reported increased verification performance of up to 1000x using M2C-Accelerator in their C-based verification suites and up to 150x in Matlab simulations when compared with the current fixed-point Matlab run-times.

M2C-Accelerator provides improved fix-point verification speeds with easy-to-read C++ code, enabling more design iterations per day in a choice of model-based design environments.

The result is significant time savings for model development and time-to-market advantage over conventional design flows.

To streamline the process of targeting DSP algorithms to ASICs and FPGAs, the 2006.1 release of AccelChip DSP Synthesis also introduces a new feature called AccelProbe.

AccelProbe assists the automated floating-point to fixed-point conversion process by providing graphical feedback, including quantised signal-to-noise ratio and quantisation histogram reports on any variable in the design.

The AccelProbe feature can be used in conjunction with either fixed-point Matlab or fixed-point C simulations.

‘Rapid verification at all levels of abstraction is the cornerstone of model-based design’, said Bradley Armstrong, AccelChip’s Vice President of Engineering.

‘To reduce risk and development time, it is imperative each model used be a derivative of the golden source so that the end product matches the original specification’.

‘Companies spend typically 10x their algorithm development time ensuring the algorithmic model, system-level model, RTL model and gate level models all represent the same design and we have seen many examples where costly re-spins were required when errors were not found up front’.

‘With M2C-Accelerator, AccelChip now provides this level of security for companies that rely on C as part of their design flow’.

Version 2006.1 of AccelChip DSP Synthesis with IP-Explorer technology, M2C-Accelerator, Export System Generator and AccelWare IP Generator toolkits are all now shipping.

Current AccelChip maintenance customers will receive the new release at no additional fee.

M2C-Accelerator and Export System Generator are available as options to AccelChip DSP synthesis.

Pricing for AccelChip DSP Synthesis starts at $15,000 for a six month time-based licence.

Pricing for M2C-Accelerator starts at $5000 for a six month licence.

Helicopter maker AgustaWestland has selected Artisan Studio as its corporate standard UML tool for software and systems development.
AgustaWestland, a leading worldwide group excelling in the design and manufacture of advanced technology helicopters for both civil and military applications, with major operations in Italy, the UK and USA, has selected Artisan Studio as its corporate standard UML tool for software and systems development. AgustaWestland companies worldwide will benefit from this corporate decision. ‘We are very impressed with Artisan Studio’s feature-set’, said Dr Ferdinando Battini, who is responsible for software practice at AgustaWestland.

‘We looked thoroughly at tools from several vendors but were immediately struck by Artisan Studio’s ease of use and ada code reversing capabilities’.

‘We have had distinct problems in the past reversing code that was written without a model’.

‘The reverser in Artisan Studio is the best we have evaluated’.

‘We are also extremely pleased with the automatic code synchroniser, which enables us to keep our UML models and Ada source code synchronised all the time’.

AgustaWestland is part of Finmeccanica, one of the largest investors in R and D in Italy, the UK and the USA, spending over 12% of its revenues.

Investing in research has enabled Finmeccanica to accumulate substantial technological knowhow, especially in the aerospace and defence sectors.

As a result of this and its highly focused strategy of international positioning and development, Finmeccanica plays key roles in every main programme and project in the strategic aerospace and defence sector, contributing its own exclusive design, development and production competence.

Jeremy Goulding, President and CEO of Artisan commented: ‘We are extremely pleased that Artisan Studio was selected by AgustaWestland as the systems and software engineering modelling tool of choice’.

‘Artisan Studio’s scalability and multi-user repository combined with its open architecture and extensibility enables project development teams to be easily integrated regardless of their size or location’.

‘AgustaWestland has successfully exploited the extensibility capabilities of Artisan Studio to create its own add-in tools as well as to customise our code generators to meet specific project requirements and further enhance productivity’.

‘This flexibility is essential for organisations as process and project requirements inevitably change in response to business, technology and customer demands’.

Increasing internationalisation is a key feature of the AgustaWestland’s business strategy.

It succeeds in some of the world’s most difficult markets, defeating formidable competitors.

The US Coast Guard uses AgustaWestland A109 Power helicopters and has chosen the AB139 for its Deepwater programme.

Phoenix Police Air Support Unit selected the new high performance single engine A119 Koala helicopter, just a few months after the delivery of their first multi-role twin engine A109 Power helicopter.

The US President will soon fly in the US-101 helicopter variant developed specifically for the American market in a joint venture with Lockheed Martin.

‘We are very proud that AgustaWestland chose Artisan Italy as a partner and Artisan Studio as the UML system and software corporate tool of choice’, concluded Carmelo Tommasi, Managing Director of Artisan Software Tools SRL.

‘Agusta in Italy and Westland in UK were the first Finmeccanica companies to adopt Artisan Studio’.

‘We are also extremely pleased that this decision will soon be extended to the Finmeccanica corporate level and all the Finmeccanica companies worldwide will be using Artisan Studio to design mission-critical systems and software’.

‘AgustaWestland and other Finmeccanica companies are an important part of the avionics and defence electronics backbone in Europe and this corporate agreement will confirm Artisan’s leadership in this strategic industry sector’.

Verum Consultants has closed its first funding round with investments from international bank ABN Amro and the Dutch Government.
Verum Consultants has closed its first funding round with investments from international bank ABN Amro and the Dutch Government. Based in the Netherlands, Verum’s expertise brings predictability to embedded software development. Its Analytical Software Design (ASD) service solution delivers measurable improvement in critical areas of software development, including time to market, product quality and product cost.

The application of Verum’s ASD services to a customer’s software development project results in a 90% reduction in defects, a 30% reduction in development costs and a 30% cut in project duration.

Verum has secured Borgstellingskredit funding, awarded to demonstrably innovative high tech businesses.

SenterNovem, the Dutch Government agency for innovation and sustainable development, ratifies the award.

The Eur 0.5 million funding is a third funded by ABN Amro and two thirds by the Dutch Ministry of Economic Affairs.

‘Verum’s management has shown the knowledge and perseverance to realise ground-breaking ideas’.

‘ABN Amro believe it’s important that such innovations are backed and that’s why the bank is more than willing to invest’.

‘The Borgstellingskredit is an excellent funding vehicle, both for the entrepreneur and the bank’.

‘The ABN Amro is currently the leader in securing this sort of funding for small and middle sised businesses’, said Jan Denis from ABN Amro Eindhoven.

Verum will use the new investment to continue to roll out its ASD service offering to original equipment manufacturers in Benelux and the UK.

Its target markets include the original equipment, automotive, medical and telecomms markets.

Its blue chip customer list includes Philips Medical Systems and the FEI Company, the world leader in nanoscale 3D characterisation.

‘This is a significant deal for Verum by completing our startup phase’.

‘This funding provides a solid platform to grow the service component of our business’, said Robert Howe, CEO, Verum Consultants.

‘Software is ubiquitous - and its complexity increasing’.

‘Cutting costs to create working, bug-free code has become a huge challenge’.

‘Verum provides a unique solution and we see this as a massive market opportunity’, Howe concluded.

The Gnat Programming Studio is a sophisticated software development environment for the Ada programming language.
AdaCore has introduced the latest and most versatile version of its Gnat Programming Studio (GPS) product, a sophisticated software development environment for the ada programming language. Incorporating a significant number of new features, this new version delivers improved usability and more powerful source navigation. It is available on the latest 64bit Gnu/Linux-based platforms, including those from SGI, HP and Intel.

Productivity-increasing improvements include a more user-friendly location view, enhanced tool tips, code completion, and new project editing capabilities.

Human interface improvements include better layout of graphical information, and the ability to export using the Scalable Vector Graphics format.

‘With this new version, GPS continues to set the pace as the industry’s most advanced Ada development environment’, said Arnaud Charlet, GPS Project Manager at AdaCore.

‘Many features are based on suggestions from customers, resulting in a practical tool that can be used to develop, manage and maintain even the largest and most complex systems’.

‘Our Gnat Programming Studio has been a success since its inception’, added Robert Dewar, AdaCore’s President and CEO.

‘Its intuitive interface, tailorability and extensibility make it an essential tool for the professional Ada programmer’.

‘With the enhancements offered in the latest release, GPS remains the integrated development environment of choice for Ada’.

GPS offers advanced features such as multilanguage support (including Ada, C and C++) and is available on a wide range of host environments for both native and cross-development, including Unix, Windows and Gnu/Linux.

An intuitive, unified visual interface, identical across all platforms, serves as a control panel to access tools from AdaCore’s Gnat Pro Ada development environment as well as from third parties, easing both development and maintenance.

As a result, GPS is particularly suited for large, complex systems requiring tool chain integration, ease of use, user customisation, and code navigation/analysis.

This latest version of GPS provides many new improvements, including: new availability on IA-64 SGI Altix, IA-64 HP Linux, IA-64 HP-UX, x86-64 Gnu/Linux platforms; new cross-reference queries; improved plug-in capabilities and python extensions; refactoring (rename entity, named parameter associations); more efficient and user-friendly locations view; improved assembly view; persistent bookmarks; version control system activities (group commit); enhanced tooltips and code completion; improved graphs (better layout, ability to export in SVG format); a new call graph tree; and project editor enhancements.

As with all Gnat Pro components, GPS is distributed with full source code and is backed by AdaCore’s rapid and expert online support.