Altera and TES Electronic Solutions have developed a novel first cost-effective reconfigurable platform for automotive display applications.
Altera and TES Electronic Solutions have developed a novel first cost-effective reconfigurable platform for automotive display applications. TES has provided both hardware and software component libraries to the application. The hardware acceleration component consists of the display controller and accelerated vector engine (D/AVE) providing increased hardware graphics display performance.

This innovative vector-based rendering engine is easy to parameterise and adds new functionality.

The software component consists of an embedded 2D/3D Graphic Multiplatform Library (eGML), which optimises high-quality real-time graphics on embedded devices with small and large display resolutions.

The library provides all functions for handling and presentation of bitmaps, frame buffer accesses and drawing of graphic primitives.

‘This single-platform solution can now be easily integrated into Altera’s devices’, said Wayne Gilbert, Strategic Marketing Director of TES Electronics.

‘It allows the first low-cost graphics controller designs offering reprogrammable parameters for a range of high-resolution automotive infotainment vector graphics applications’.

‘Our partnership with TES means a single, reparameterisable graphics platform can address most applications’, said Jeff Lamparter, Director of Altera’s Automotive Business Unit.

‘This vector rendering engine allows designers to quickly parameterise various features such as TFT, render quality (pixel) and VGA on any of Altera’s FPGAs to target graphics-hungry applications in the automotive sector’.

‘There is now a clear road to living room-like graphics in a host of previously cost-constrained applications’.

Previously, designers were forced to use microcontrollers with integrated graphics and dedicated graphics controllers for specific applications.

This necessitated separate system designs and development delays incurred by semi- or full-custom silicon.

This TES/Altera integration results in systems generating graphic output exceeding traditional systems and providing substantial power and cost savings while dramatically cutting system development time versus ASIC or ASSP implementations.

Altera’s programmable technology is being incorporated into advanced automotive applications, including driver assistance, infotainment and gateways.

In response to the exponential growth in the complexity of automotive digital systems, Altera offers a powerful design platform that delivers a flexible, low-risk design path for reducing complexity and optimising cost-efficiencies.

The Diamond Standard family of processor cores comprises a set of six off-the-shelf synthesisable cores that range from area-efficient, low-power controllers to high-performance DSPs.
Tensilica has introduced the Diamond Standard family of processor cores, a set of six off-the-shelf synthesisable cores that range from area-efficient, low-power controllers to high-performance DSPs, all of which lead the industry in their respective categories both in lowest power and highest performance. The Diamond Standard processors are supported by an optimised set of Diamond Standard software tools and a wide range of industry infrastructure partners. They are available directly from Tensilica and through a growing list of ASIC and foundry partners.

This announcement provides Tensilica with the broadest range of off-the-shelf processors in the industry, with the six Diamond Standard cores plus an almost infinite number of processor configuration possibilities for those customers requiring optimised, application-specific processors with Tensilica’s award-winning Xtensa configurable processor family.

Tensilica is now seeing significant shipments from production volumes in SoCs for cellphones, printers and other consumer and communications devices, where its cores serve not only traditional RISC controller functions, but often are used as an alternate means of implementing high-performance, low-power compute functions previously implementation only with risky and complex RTL logic blocks.

The first six members of Tensilica’s Diamond Standard processor family cover a wide range of system requirements.

The Diamond 108Mini is an ultra-low-power, cacheless RISC controller with rich interrupt architecture and minimal gate count for lowest silicon cost.

The Diamond 212GP is a flexible mid-range RISC controller with instruction/data caches and user selectable local memory sizes, providing 50% better DMIPS performance and 30% lower power than an ARM9.

The Diamond 232L is a flexible mid-range RISC CPU core with full MMU (memory management unit) for Linux OS support.

The Diamond 570T is a high-performance three-issue static superscalar CPU core that beats the ARM11-based systems by more than 2x in EEMBC benchmarks.

The Diamond 330HiFi is a low power 24bit audio processor for all popular audio and speech codecs, based on the market-leading Xtensa HiFi 2 audio engine.

And the Diamond 545CK is the highest performance licensable DSP on the market with a three-issue VLIW (very long instruction word) processor with an eight-MAC SIMD DSP.

All these processor cores are available with Tensilica’s Diamond Standard software tool set, including a high-performance optimising C/C++ compiler, instruction set simulator, Eclipse-based graphical development environment, and complete Gnu-based tool chain with assembler, debugger, profiler, and linker.

An amba bus interface is optional for all cores.

Tensilica has already benchmarked several of these processor cores and received top marks.

The Diamond 545CK, based on the Xtensa LX used in the original benchmark, achieved the highest score recorded to date for a licensable processor core on the BDTI Benchmarks by Berkeley Design Technology, (BDTI).

Its BDTIsimMark2000 score of 3490 at 220MHz is 30% faster than the score for the next-fastest licensable core benchmarked by BDTI, the CEVA-X1620.

Also, the Diamond Standard 545CK is over twice as energy efficient as any other core benchmarked by BDTI to date.

EEBMC benchmark scores for the Diamond 570T far surpassed both the ARM1026EJ-S and the ARM11 class CPUs (Freescale iMX31 implementation with ARM1136J-S) in EEMBC’s Consumer, Networking, Telecom and Office Automation tests.

The Diamond 570T core delivers 2.3x the performance of the ARM11 in less than half the silicon area.

Additionally, the actual benchmark code size of the Diamond 570T is only 80% the amount of code required by the ARM1026EJ-S for the exact same EEMBC algorithms.

Tensilica will expand its customer base with the Diamond Standard processors in two ways.

First, because the Diamond Standard processors will be distributed by leading ASIC and foundry providers, Tensilica will be able to reach more potential customers.

Secondly, the customer base should expand because Tensilica offers a better combination of lower price, higher performance and lower power compared with other competing processor cores.

The Diamond Standard processors complement Tensilica’s existing Xtensa configurable processor product family.

Because Diamond Standard cores are based on Tensilica’s Xtensa configurable-processor technology, designers using Diamond Standard cores can easily extend the performance of their future designs using Tensilica’s Xtensa processor offerings.

‘We couldn’t have launched this product line several years ago when Tensilica was new and our processor architecture relatively unproven’, stated Chris Rowen, Tensilica’s President and CEO.

‘But now we have over 80 blue-chip customers in many diverse markets, and mainstream designers are asking their ASIC suppliers for Tensilica’s processors’.

‘The Diamond Standard processors are ideal for this new ASIC and foundry distribution channel’.

‘Based on our experience in hundreds of designs, we feel we have predefined these cores to match major market segments’.

‘Tensilica has made some impressive strides lately’, added Tony Massimini, Chief of Technology, Semico Research.

‘The company’s recent design wins portend strong potential growth’.

‘Semico foresees healthy growth for embedded cores over the next several years due to consumer and communications markets’.

‘Tensilica has been focusing on these high growth markets’.

‘Semico believes that embedded cores will grow due to the added functionality offered by configurable cores’.

‘Tensilica is one of the companies driving this trend’.

Tensilica’s new Diamond Standard processor family is based on its proven Xtensa configurable and extensible processor architecture, used in over 250 chip designs by over 80 customers.

Tensilica’s engineers used the same Xtensa processor generator technology as its Xtensa processor customers use to create these optimised standard configurations.

Tensilica’s automated processor generator technology completely verified the configurations and produced the matching software tool chain.

By using the proven Xtensa architecture, customers can be reassured that, if they like one of these Diamond Standard processors but would prefer a more tailored processor solution for their application, they can switch to using Xtensa configurable processors and maintain full software compatibility.

Many ASIC customers prefer the simplicity of purchasing from their ASIC or foundry silicon provider a processor core as part of the NRE (nonrecurring engineering) expense of their SoC design.

Now that Tensilica’s Xtensa processor has met with broad success, customers are requesting Tensilica’s processors from their ASIC suppliers.

That’s why these partners were interested in Tensilica’s Diamond Standard family.

Tensilica has signed up NEC Electronics, Global Unichip and SMIC as its initial ASIC and foundry partners, and the company expects to sign up several other ASIC partners this year.

This should significantly expand Tensilica’s reach into the mainstream ASIC design community.

Tensilica is providing a proven infrastructure for its Diamond Standard processor core family.

This infrastructure includes software development tools directly from Tensilica as well as: operating system support for Linux from Monta Vista, the Nucleus Plus OS from the Accelerated Technology division of Mentor Graphics, and micro-iTron from Sophia Systems; coverification support for Mentor’s Seamless product; ICE (in-circuit emulation) from Sophia Systems and Yokogawa Digital Computer JTAG probe and Debugging support from Macraigor Systems, Sophia Systems and FS2; EDA tool support from Synopsys, Cadence and Magma; and the industry’s broadest lineup of application packages for audio support of the Diamond Standard 330HiFi.

Tensilica’s new Diamond Standard family of processors is available now.

Pricing for the Diamond 108Mini starts at $75,000 for a single-use licence with 5 cents per core royalty.

VTech’s V.Flash home edutainment system is the first consumer electronics product to use the recently announced LSI Logic Zevio application processor architecture.
VTech’s V.Flash home edutainment system is the first consumer electronics product to use the recently announced LSI Logic Zevio application processor architecture. The Zevio architecture and 3D graphics technology, codeveloped with Koto, are enabling VTech Electronics to offer a home edutainment system that allows children the ability to learn as they play in a dynamic and interactive 3D-gaming environment. VTech is one of the world’s leading suppliers of electronic learning products including its popular V.Smile TV learning system.

Koto is a leading manufacturer of unique entertainment devices and their related technologies.

‘With expertise in their respective technologies, LSI Logic and Koto are effective partners who are providing us with a complete solution - including development systems, hardware and software support - to meet the requirements of V.Flash’, said Julia Fitzgerald, Vice President of Marketing, VTech Electronics North America.

‘The result is a unique, 3D home edutainment system that we believe will be very successful this holiday season’.

With the LSI Zevio platform, VTech is able to offer a unique TV-based learning system for less than $100.

Combining video gaming, CD playing and 3D graphic visual entertainment into a compact, stylish console, VTech’s V.Flash creates a dynamic and exciting interactive learning experience.

V.Flash is expected to be available in the fall of 2006, with six licensed game titles that will be sold separately.

‘At CES in January, we announced plans to expand into the digital consumer appliances market with our Zevio architecture’.

‘VTech’s V.Flash Home Edutainment System validates the benefits of the Zevio architecture for next-generation consumer devices’, said Tim Vehling, Vice President of Marketing, Consumer Products Group, LSI Logic.

‘Innovative products like V.Flash showcase the cost-effective 3D graphics capabilities that we co-developed with Koto’.

Building on its substantial consumer standard product and custom solutions knowledge, LSI created the Zevio architecture to enable the optimal price-power-performance balance for digital consumer appliances such as GPS navigation systems, electronic toys, edutainment applications, and personal media players.

By providing development support tools and preverified, consumer-specific IP for companies like VTech, the Zevio architecture reduces design complexity and time to market.

Koto, developer of the WonderSwan handheld gaming system in Japan, collaborated on the creation of the Zevio 3D graphics technology to reduce complexity and help fuel demand for 3D features in a variety of consumer electronics products.

Semiconductor Manufacturing International Corp, Virage Logic Corp and Tensilica are collaborating to provide hard macro versions of Tensilica’s new Diamond Standard processor cores.
Semiconductor Manufacturing International Corp, Virage Logic Corp and Tensilica are collaborating to provide hard macro versions of Tensilica’s new Diamond Standard processor cores. The processors will be implemented using Virage Logic’s silicon-proven IPrima Foundation Platform IP and will target SMIC’s 130nm process technology. ‘Tensilica’s new Diamond Standard processor cores are among the industry leaders in high performance and low power’, stated Paul OuYang, Vice President of Design Services at SMIC.

‘By implementing the cores with Virage Logic’s IPrima Foundation Platform IP, the Diamond Standard processors should be reliable and easily manufacturable, thus reducing risk and shortening the overall design cycle’.

‘We believe that a large number of our customers will be interested in using these cores’.

‘We are pleased to work with Tensilica and SMIC to develop hard macro versions of the Diamond Standard processors’, said Adam Kablanian, President and CEO, Virage Logic.

‘By utilising the embedded memories and standard cell libraries in our IPrima Foundation for SMIC’s 130nm process, Tensilica’s worldwide Diamond Series processor customers will be able to gain both high performance and low power advantages’.

‘SMIC is one of the leading semiconductor manufacturers in the world, and Virage Logic produces technically superior semiconductor IP platforms, so we are delighted to work with both companies to provide hardened versions of our Diamond Standard processors’, stated Chris Rowen, Tensilica’s President and CEO.

‘We believe there will be a strong interest in China, where we believe our ultra-low-power controller cores and the unique Diamond 330Hifi audio processor to be very good fits with the rapid growth of consumer electronics design firms’.

Under the agreement, SMIC will provide complete design and manufacturing services - including incorporation of the Diamond Series hard macros into design databases - for companies requiring low-power, high-performance processors and DSPs in SMIC’s 130nm process.

The hard macro solutions resulting from the collaboration will enable systems and semiconductor companies to use SMIC’s foundry process with minimum integration cost, accelerated integration time and reduced risk.

A hardened core is a complete and tested physical design of a processor core, which can be included into an ASIC design.

MIPS Technologies has appointed Kate Hunt Rundle to the position of Vice President, General Counsel.
MIPS Technologies has appointed Kate Hunt Rundle to the position of Vice President, General Counsel. She reports to President and CEO John Bourgoin. Rundle, who has more than 20 years experience in Silicon Valley, including intellectual property (IP) licensing, protection and litigation, is responsible for all of MIPS Technologies’ legal affairs.

Rundle succeeds Sandy Creighton, who assumes the position of Vice President, Human Resources and Corporate Administration.

Rundle joins MIPS Technologies from Sun Microsystems, where she spent more than eight years handling legal affairs, most recently as deputy general counsel and managing senior director of the Global Law Network for Shared Services.

Prior to her role at Sun, she served as intellectual property counsel at The 3DO Company and, for 11 years, was an attorney at Wilson, Sonsini, Goodrich and Rosati, where she provided IP licensing and other services to a broad range of technology companies.

Rundle earned her JD from the University of California, Hastings College of the Law, San Francisco, after graduating magna cum laude from the University of California, Berkeley.

‘Kate brings a wealth of experience and insight to the MIPS legal team’, said John Bourgoin, President and CEO.

‘Her expertise in vital areas of our business, including the licensing and protection of intellectual property on a global scale, will allow her to play a pivotal role in MIPS Technologies’ continued growth’.

Renesas has licensed the ARM11 MPCore multiprocessor for use in its large scale integrated (LSI) semiconductor solutions.
Renesas has licensed the ARM11 MPCore multiprocessor for use in its large scale integrated (LSI) semiconductor solutions. As computing moves into an era of ubiquitous networks, superior processing power is becoming critical for driving new features in PCs, digital electronics, and mobile telephones. However, as improved performance requires greater processing speeds, processors have a tendency to exceed power-consumption tolerances.

One solution currently gaining ground is the multicore chip architecture, in which multiple CPU cores are mounted on a single chip.

By licensing the ARM11 MPCore processor, Renesas can significantly expand its SoC core line-up.

‘In its bid to create innovative, comprehensive solutions, Renesas Technology has been developing buses and memory architectures that deliver high-speed data transmission and memory, as well as software and middleware that drive these systems’ performance, based on CPU cores and IP systems’, said Hideo Inayoshi, Senior Vice President and Executive General Manager of Renesas Technology’s Systems Solution Business Group.

‘While Renesas Technology already offers powerful SuperH CPU cores, in response to our customers’ requests for a broader product range we are complementing our products with ARM’s proven line of processors’.

‘Our partnership with ARM gives us an optimal solution, enabling us to provide a wide range of CPUs from both Renesas Technology and other manufacturers’.

‘The choice by Renesas Technology, a world leader in technology, to license the ARM11 MPCore symmetrical multiprocessor further proliferates the adoption of ARM’s industry-leading technology’, said Takafumi Nishijima, President of ARM Japan.

‘The MPCore processor is clearly an outstanding solution for the growing consumer device market, as well as other markets that require multimedia processing and simultaneous operation of multiple applications’.

‘This licensing agreement will play a key role in accelerating adoption of ARM processor technology in Japan and throughout the world’.

Renesas Technology previously licensed the ARM946E-S processor and the ARM1136JF-S processor.

As part of Renesas’ multicore strategy, the present licensing agreement forms part of Renesas Technology’s bid to broaden its product portfolio in addition to its own CPU core processors and offer customers greater choice.

The ARM11 MPCore processor’s open architecture is a proven solution.

Its solid development environment, including test chips and an evaluationboard, enables developers to create robust system solutions quickly.

Renesas plans to roll out its first products using the ARM11 MPCore processor in 2008, with a primary focus on digital home electronics and office-automation systems.

As multicore architectures assume ever-increasing importance in a fast-changing market, ARM and Renesas Technology view their partnership as a key to their success.

Renesas Technology’s leadership in advanced SoC marketing, development, and mass production is ideal for ARM’s advanced CPU core technologies.

This forms a solid basis for the companies’ collaboration in the development of pioneering semiconductor products.

ARM Advantage physical IP is made available on the 65nm generic process for the Common Platform.
ARM is collaborating with IBM, Chartered semiconductor manufacturing and Samsung Electronics to offer the ARM Advantage products, part of its Artisan family of physical IP, on the 65nm generic process for the Common Platform. The agreement furthers the companies’ commitment to enable multi-sourcing strategies and enhanced design portability for customers of the three manufacturing leaders. It extends the design enablement support from ARM offered for the Common Platform, building on the initial availability of physical IP for the 90nm process with IBM and Chartered.

The low-power ARM Metro products, part of its Artisan family of physical IP, for IBM, Chartered and Samsung at the 65nm low-power process was announced last year.

‘The Common Platform model has proven to be an attractive choice for many customers who want not only leading-edge manufacturing capacity, but also a low-risk, flexible approach to managing their sourcing strategies’.

‘Adding this IP support from ARM makes the common 65nm process that much more accessible across all three companies, and provides a broader range of options for our mutual customers’, said Steve Longoria, Vice President, semiconductor technology Platform for IBM Systems and Technology Group.

ARM Advantage IP provides high-speed, low-power performance to meet a wide range of applications in consumer, communications and networking markets.

The Advantage and AdvantageHS standard cells include power management kits that are characterised for multiple transistor threshold voltages.

Five Advantage memory compilers are offered with advanced power saving features.

The I/O products include multiple configurations supporting 1.8, 2.5 and 3.3V systems.

The suite of products is characterised for timing and power over an extended range of voltages, enabling designers to perform accurate pretapeout simulation of multiple-voltage designs.

The Advantage IP includes ARM’s extensive set of views and models providing integration with many of the industry’s leading electronic design automation (EDA) tools.

Additionally, the IP incorporates the combined expertise of ARM, IBM, Chartered and Samsung in addressing the complexities of design for manufacturability of advanced 65nm technology.

A complete set of ARM physical IP products are expected to be available second quarter of 2006 for download from ARM’s website, free of charge, to customers in the 65nm process.

‘The Common Platform is addressing designers’ requirements for faster transitions to 65nm, but with the flexibility and risk reduction of an optimised manufacturing process that is supported by multiple foundries simultaneously’, said Kevin Meyer, Vice President of Worldwide Marketing and Platform Alliances at Chartered.

‘Extending the ARM Advantage products to the IP portfolio that supports our joint 65nm processes helps position the Common Platform as a very compelling choice for early adopters as they design their next-generation, cutting-edge products’.

‘Today’s system-on-chip (SoC) design or IP-based ASIC design requires access to a selection of highly qualified IP that is silicon-proven and easy to integrate’, said Dr Ben Suh, Vice President of ASIC/Foundry Business Development, System LSI Division, Samsung Electronics.

‘Samsung is pleased to provide proven ARM Advantage physical IP supported by the Common Platform at 65nm that will give customers chip design-to-manufacturing solutions that meet their business objectives’.

‘The addition of the ARM Advantage products in the 65nm generic process significantly expands the choices customers have for their 65nm design’, said Neal Carney, Vice President of Marketing, Physical IP, ARM.

‘SoC designers across the industry will have access to a suite of comprehensive IP and process technologies that address low-power and performance requirements that will differentiate their end products’.

Imagination Technologies has opened an office in Taipei to serve the world class Taiwanese fabless industry.
Imagination Technologies has opened its first Taiwanese office, in Taipei, to serve the world class Taiwanese fabless industry. Maxwell Lin, formerly of EDOM and Cirrus Logic has been appointed as Imagination Technologies’ Director of Sales for Taiwan. Imagination Technologies provides technology to partners including ARM, Centrality Communications, Freescale, Frontier Silicon, Intel, Philips, Renesas, Samsung, Sharp, Sunplus and Texas Instruments.

Launching its Taiwan office, Imagination Technologies, in collaboration with the Industrial Technology Research Institute (ITRI), is holding seminars in Hsinchu and Taipei, to introduce its silicon intellectual property (SIP) through presentations and demonstrations.

Demonstrations include: solutions for digital and analogue TV, including DVB-T, multistandard SD and HD decode, image enhancement and multi-standard demodulation; solutions for multistandard mobile digital TV (T-DMB and DVB-H on one device); 3D graphics and video for multimedia in mobile phones, PDAs and PMPs; and DAB digital radio and digital audio.

Says David McBrien, VP Business Development, Imagination Technologies: ‘Semiconductor IP cores are the most effective way of accelerating the development of competitive SoC devices while reducing business risk’.

‘We create flexible, competitive and preverified technology that partners may not have the time or expertise to develop themselves in areas such as multistandard demodulation, HD video and 3D graphics’.

‘This enables our partners to add value and differentiate in technology areas where they are strong, providing market leading solutions in a timely manner’.

The ability to license complete SoC platform solutions that are integrated, optimised and preverified also allows partners to enter new applications - digital radio, mobile TV, 3D UI, PMP, IPTV etc - ahead of their competitors.

Imagination Technologies’ seminars will include an address by Dr CW Jen, Chairman of the Taiwan SoC Consortium as well as expert insight from Imagination’s team into key application areas for mobile graphics, video, audio and TV technologies.

The seminars will take place on 6th March 2006 at the Grand Formosa Regent, Taipei and on 8th March at the Ambassador Hotel, Hsinchu.

A new partnership programme aims to build a wide portfolio of best of breed applications that are pre-integrated on TTPCom’s Ajar platform.
TTPCom has launched its Ajar partnership programme, aiming to build a wide portfolio of best of breed applications that are pre-integrated on its Ajar platform, the definitive mobile applications suite for mobile phones. Participating organisations are able to access the handset mass market more rapidly and the pre-integration of the technologies means that partners also benefit from TTPCom customers’ accelerated times to market and revenue. High-end multimedia applications have traditionally been integrated into smart phones which represent only 10% of the market.

The challenge for many application providers is to penetrate the higher volume, mass-market, feature phone segment.

Collaboration with TTPCom provides an effective route into this growing market.

In addition, partners benefit from a greatly reduced support burden as a single integration with TTPCom’s Ajar platform gives them instant access to multiple hardware platforms and TTPCom’s 50-plus customers.

This dramatically reduces partners’ operating, support and maintenance costs.

Commenting on the programme, Morten Iversen, Director of Partnership Programmes at TTPCom said: ‘Our close working relationships with operators, handset manufacturers and content providers allow us to understand the increasing challenge of delivering handsets with multiple combinations of complex technologies’.

‘Our solution is Ajar’s semi-open architecture which enables new technologies to be incorporated quickly’.

‘The experience gained from working with the 20 best-of-breed technologies already pre-integrated onto Ajar has helped us formalise the programme to deliver greater commercial benefit to both customers and partners’.

‘We aim to continue to expand the programme and invite new technology partners to provide our customers with even more choice’.

‘In the ultracompetitive mobile market, manufacturers and service providers are looking for ways to distinguish themselves with proven solutions and intuitive functionality’, said William Clement, Senior Marketing Manager, Europe for Tegic Communications.

‘TTPCom has stepped up to satisfy the growing demand among carriers and consumers with a business model that enables them to provide best-in-class technology - including T9 Text Input’.

‘We are pleased to be selected by TTPCom as their preferred Java partner for their Ajar platform’, said Jean-Claude Martinez, COO of Esmertec.

‘Through this close collaboration with TTPCom, we are able to deliver a cutting edge Java solution on Ajar to handset manufacturers for mass-market feature phones, and we look forward to working closely with TTPCom to enable further innovative solutions’.

New technologies added to the scheme will join leading mobile applications including: Esmertec’s Java, WAP from Teleca and Jataayu, voice recognition from Scansoft (formerly ART), games from Kayak Interactive, AAC+ from Coding Technologies and predictive texting capabilities from Zi and America Online ’s Tegic Communications to name but a few.

PrimeCell Amba 3 AXI static memory controllers support a comprehensive array of new and emerging memory devices, including NAND Flash, NOR Flash, SRAM and high-performance pseudo-SRAM.
ARM has developed a new range of PrimeCell amba 3 AXI static memory controllers to support a comprehensive array of new and emerging memory devices, including NAND Flash, NOR Flash, SRAM and the high-performance pseudo-SRAM (CellularRAM) devices. The PrimeCell AXI static memory controllers provide system designers with a single IP solution for systems using CellularRAM and Flash memory. Combined with the existing PrimeCell AXI dynamic memory controller supporting DDR and Mobile-DDR, and with DDR2 support under development, ARM is now able to provide a complete, high-performance memory controller solution for a wide range of applications.

The PrimeCell AXI static memory controller is configurable, removing the need to compromise the system characteristics whilst retaining the low cost of ownership and low risk of preverified PrimeCells.

To complement the product, a high performance simulation model is also available.

This model enables designers to analyse their system’s performance with Amba Designer and obtain the information required to select an optimal configuration.

‘The extensive range of supported memory types, combined with ARM’s Amba AXI expertise and ability to deliver configurable IP, makes the PrimeCell AXI static memory controller the perfect fit for the TTPCom CBEmacro dual mode modem design’, said David McTernan, Product Marketing Director at TTPCom.

‘CBEmacro enables extremely compact and performance optimised Edge/WCDMA or Edge/HSDPA baseband silicon’.

‘System integration of a modem with a multimedia applications processor is eased by the use of the latest Amba 3 AXI high-performance system components to effectively share the memory interface between modem and application functionality’.

In addition to the new Amba 3 AXI memory controllers, ARM’s support for new and emerging memory devices is also extended to Amba 2 AHB system designers through the release of a new series of AHB memory controller products, preconfigured to support a range of typical product requirements.

‘By working with the number one provider of CellularRAM memory, ARM combines Micron’s expertise in memory design and technology with their system knowledge and configurable PrimeCells to ensure efficient and effective memory controllers’, said Rene Hartner, Micron Technology’s Director of Mobile DRAM Marketing.

‘The availability of ARM’s PrimeCell static memory controllers enables chip designers to fully exploit the benefits of Micron’s low power CellularRAM product family’.

‘Integrating third party IP such as ARM’s configurable PrimeCell memory controllers into our ASIC offerings allows us to provide our customers with a broad choice of IP solutions to meet their design requirements’, said John Jansen, Director of Platform Design, Agere Systems.

‘The configurability of the PrimeCell AXI static memory controllers, in conjunction with the powerful Amba Designer system design tool, allows engineers to select the optimal performance and sise for each design’, said Jonathan Morris, Fabric IP Business Unit Manager, ARM.

‘These new products enable accelerated time to market, and provide SoC designers with a flexible and efficient external memory interface for their products’.

The Amba 3 AXI static memory controllers extends the fabric IP that unleashes the performance of ARM processors such as MPCore, ARM1176 and Cortex-A8.

The system architecture of the SoC can be explored and optimised using Amba Designer and SoC Designer.

The ARM PrimeCell AXI static memory controller series is available to license today.

The ARM PrimeCell AHB memory controller series is also available for immediate licensing.