New packaging options for the low-cost Cyclone II FPGA family provide designers of high-volume applications with even lower-cost programmable solutions and smaller form factors.
Altera has introduced new packaging options for its low-cost Cyclone II FPGA family, providing designers of high-volume applications with even lower-cost programmable solutions and smaller form factors. The new packages meet the needs of customers who are designing Cyclone II devices into low-cost applications never before addressed by FPGAs. The Cyclone II EP2C20 device is now available in the low-cost 240-pin quad flatpack (QFP) package, and the EP2C35 and EP2C50 devices are available in the 19 x 19mm, small form factor 484-pin Ultra FineLine BGA (UFBGA) package.

‘Altera maintains close working relationships with its customers from the product definition stage through when a new device family begins shipping’.

‘This enables us to learn the most about how our devices are being used and which features customers need most’, said Steve Mensor, Altera’s Senior Director of Product Marketing for Low-Cost FPGAs.

‘As more Cyclone II devices are being adopted into high-volume applications, the availability of the QFP and UFBGA packages will allow designers to realise lower total costs and to fit more functionality into a smaller board area’.

The QFP package is designed for easier PCB assembly, resulting in significant cost savings for Cyclone II users.

The EP2C20 device in the 240-pin QFP package has 142 user I/O pins and is the optimal low-cost package for PCBs with few board layers.

The UFBGA’s 0.8mm ball pitch allows for a significantly smaller device footprint - 30% smaller than the equivalent 1.0mm ball pitch BGA package - while still providing over 50,000 logic elements for designers.

LeapFrog Enterprises reduced costs and increased flexibility in the manufacturing process for its new Leapster L-MAX learning game system by integrating Altera MAX II CPLDs into the learning platform.
LeapFrog Enterprises reduced costs and increased flexibility in the manufacturing process for its new Leapster L-MAX learning game system by integrating Altera MAX II CPLDs into the learning platform. MAX II devices enable the Leapster L-MAX handheld to connect to a television, providing an interactive big-screen learning experience for four- to ten-year-olds. ‘The MAX II device helps us stay competitive in the extremely price-sensitive consumer electronics market’.

‘We have been able to implement the digital signal processing more economically than with alternative solutions and reduce costs at the manufacturing level’, said Mike Chai, Senior Vice President of Research and Development for LeapFrog Enterprises.

LeapFrog uses the MAX II device to convert the display information for the Leapster L-MAX handheld into TV-compatible video signals.

In similar applications, a digital signal processor often performs this function.

The low cost of the MAX II device family enabled LeapFrog to use a CPLD to accomplish the same function at a lower price.

LeapFrog’s decision to use MAX II devices highlights the growing trend toward the use of Altera’s programmable logic devices to integrate functions that would otherwise be performed by general-purpose or application-specific devices.

‘Using programmable logic as an alternative to an ASIC or ASSP provides product developers with compelling advantages in terms of flexibility and cost’, said Danny Biran, Vice President of Product and Corporate Marketing at Altera.

‘As this trend continues, Altera’s leadership in low-cost programmable logic devices will further drive the adoption of our solutions by consumer electronics manufacturers, and in turn support the proliferation of exciting new products like the Leapster L-MAX learning game system’.

HardCopy structured ASICs from Altera have been used in the IPX-5100, a modem designed by Efficient Channel Coding (ECC) for broadband Internet access through satellites.
Structured ASICs are a new class of devices that address the burgeoning costs of developing traditional ASICs and the time taken to obtain the first fully functional devices. This article describes how HardCopy structured ASICs from Altera have been used in the IPX-5100, a modem designed by Efficient Channel Coding (ECC) for broadband Internet access through satellites. The IPX-5100 interfaces with conventional geostationary satellites as well as the new iPStar-1 satellite providing broadband access rates up to 8Mbit/s download and 4Mbit/s upload.

The IPX-5100 uses ECC’s adaptive coding and modulation (ACM) technology to dynamically change the channel coding and modulation technique on-the-fly according to the time-varying channel conditions.

These methods dramatically improve the satellite system capacity by customising the link to an individual IPX-5100, allowing optimised use of the limited satellite bandwidth.

User traffic can be transmitted in at as high a modulation level in, combination with as high a code rate, as the instantaneous link condition allows and the strongest code and modulation should only be used to keep reliable data transmission when link is in its worst condition.

Effectively, the adaptive scheme significantly improves the average information throughput per satellite transponder.

The result of these efforts is the first satellite ACM-enabled system iPStar, offered by Shin Satellite Public Company (Asia’s second largest satellite system operator).

Due to efficiencies enabled by the combination of the iPSTAR-1 satellite and the IPX-5100 ACM technology, the iPStar system can now provide broadband Internet connectivity to consumers and small-businesses competitively with cable modem and DSL services.

Initially the IPX-5100 modem was designed with an Altera FPGA to prototype and verify the functionality of ECC’s ACM technology.

Additionally, using the prototype, ECC was able to field trial and qualify the IPX-5100 addressing the iPStar system requirements.

The next step was to move to a lower cost solution once field qualifications were approved and the terminal was ready for medium-volume production.

There are merits to considering up-front what devices to use beyond the prototyping phase.

An ASIC or a conversion ASIC (ASICs derived through conversion of an FPGA netlist) requires synthesis or resynthesis of the design, generating a netlist different than the one used to prototype.

This difference adds risk and could increase costs as well as impair market-entry plans for the product should the first silicon be not functional.

It would be nice to have a path to seamlessly migrate the prototype-proven netlist to a device suitable for high-volume production.

ECC evaluated various structured ASICs and conversion ASICs, but found that only HardCopy devices supported such a requirement.

The migration of the design from prototype to medium volume production was aided by pin-compatibility between FPGA and the HardCopy device.

Choosing the right I/O and package not only helped ECC to replace the FPGA with the HardCopy device, but also vastly eased the re-qualification of the IPX-5100 modem.

ECC used a combination of Altera’s and third-party software to prototype the design, perform physical synthesis and static timing analysis, and generate the design database to transfer to Altera for migration to the structured ASIC.

Having an integrated design environment which supports synthesis and simulation tools allowed ECC to leverage its existing tool-suite and take the design from prototype to silicon in the quickest possible time.

Coding to synchronous design principles facilitated several design steps including synthesis, timing analysis and testability of the device.

Although it is always enticing to get that ‘extra 1MHz’ through a code segment that violates these established rules, inadvertent usage can considerably hamper verification and testability issues.

ECC used the design assistant feature in Altera’s Quartus II software to find any such violations in the design, make an analysis and fix if necessary.

Knowledge of such violations prior migration helped ECC to ensure that the design can be migrated smoothly in the quickest possible time, and eventually test the manufactured devices.

HardCopy devices use typical ASIC design backend flows to translate a signed-off netlist to layout.

Clock tree synthesis, parasitic extraction, back-annotated static timing analysis (STA) and formal verification are some of the key events in the migration process that Altera performed to ensure the layout maps to the proven design and also mirrors close to the manufactured silicon in functionality and performance.

The IPX-5100 modem needed higher performance from the HardCopy devices compared with the FPGA prototype.

The inherently faster nature of the HardCopy devices over their FPGA counterparts (up to 63% faster) due to the absence of programmability and shorter interconnect lengths, stemming from a smaller die size, ensured that the HardCopy device met the specifications of IPX-5100 thus satisfying ECC’s data-rate goals.

Any timing violations discovered during back-annotated STA were fixed with proper buffer insertions and routing constraints.

Once ECC signed-off on the final timing, the database was taped-out for manufacture.

SRAM-based FPGA devices typically require a configuration device that programs the FPGA on power-on and accommodates for rapid design changes.

However, once the design has stabilised, the programmability is unnecessary (and hence the configuration device).

HardCopy devices provide configuration emulation features which not only enabled ECC to retain its existing board and architecture but also voided any necessity to change the software.

The design was checked by ECC and Altera’s design engineers to see if it violated industry-standard design for testability (DFT) techniques.

The embedded test logic such as scan, memory built-in self test (BIST) and JTAG structures provided vehicles to test the manufactured device.

Further, ECC did not provide any functional vectors to Altera as the design used structural testing through ATPG vectors resulting in a high quality device.

ECC prototyped its modem and MAC processor design in an FPGA, then migrated their verified design to a HardCopy structured ASIC device to reduce design time, lower manufacturing costs, and increase performance.

HardCopy devices are manufactured as base arrays up to a certain process step ahead of specific designs.

Once the database was ready, design information was routed on the parked wafers using the top three metal layers.

Packaged and tested samples were available in less than seven weeks.

When ECC replaced the FPGA on the board with the HardCopy device, the IPX-5100 worked flawlessly, meeting the system requirements.

The seamless migration of the prototype-proven design delivered fully-functional first silicon, enabling the IPX-5100’s quick entry in the market place with minimum development costs.

Actel has published new results showing that its nonvolatile field programmable gate arrays offer up to 4000 times better power-on response time than competing SRAM-based FPGAs.
Actel has published new results showing that its nonvolatile field programmable gate arrays offer up to 4000 times better power-on response time than competing SRAM-based FPGAs. Additionally, Actel’s live at power-up (LAPU) single-chip FPGAs drive down total system costs by eliminating the need for additional power-up and initialisation circuitry. The LAPU nature of Actel’s nonvolatile FPGA technologies makes them optimal solutions for automotive, consumer, medical, military and other applications that require immediate operation as well as low total system cost.

To help simplify selection of LAPU devices Actel has created a new LAPU classification system to quantify initialisation capabilities of various semiconductor solutions.

Further information regarding these results and Actel’s LAPU classification system is outlined in a new live at power-up white paper published by Actel and available via the company’s online LAPU resource centre.

The Actel LAPU device classification system has three levels: live at power-up (Level 0), live after power-up (Level 1) and live after system initialisation (Level 2).

Level 0 LAPU devices are operational between power-on and power-up (the time at which the applied voltage has reached the lower limit of system voltage and is stable) and include Actel’s devices and other nonvolatile FPGAs, ASICs and some ASSPs.

Level 1 LAPU devices require a configuration download from internal memory but are operational before system initialisation and include ASSPs, Flash-in-package SRAM FPGAs and most CPLDs.

Level 2 LAPU devices are operational only after the initialisation of system clocks, resets, interfaces and memories and include most SRAM-based FPGAs and processors.

‘FPGAs based on volatile SRAM make system start-up complex and expensive due to their need to load configuration data from external memory before they are operational’, said Martin Mason, Director of Product Marketing at Actel.

‘There is a lower cost and simpler solution available using Level 0 LAPU devices like Actel’s FPGAs, which dramatically simplify application startup and provide significant reductions to total system cost, PCB size, power consumption and increase system reliability and security’.

Live at power-up FPGAs are the only devices that can assist in system start-up tasks, system configuration and supervision during voltage ramp-up, which can result in total system cost savings of 50% or more.

Martin Alcock, President and CEO of Integen Technologies said: ‘By using Flash-based, live at power-up devices instead of SRAM-based FPGAs in our hospitality products, we were able to reduce our overall system component count by eliminating not only the need for external program memories but also reducing the design requirements of our power supplies at the same time’.

‘We value the live at power-up capabilities offered by Actel’s single-chip FPGAs, and we plan to leverage this technology for future designs’.

Actel’s online LAPU resource centre provides designers with information regarding power-up issues for their next FPGA design, including links to white papers, product information brochures, application notes and other technical information via Actel’s website.

Lattice Semiconductor has appointed Steve Mugford as Country Sales Manager for the UK and Ireland.
Lattice Semiconductor has appointed Steve Mugford as Country Sales Manager for the UK and Ireland. Prior to his appointment Mugford held several senior sales positions with Cypress Semiconductor, most recently as Marketing Manager for memory products. Prior to this he was a Senior Development Engineer with GEC Marconi Avionics.

Commenting on Mugford’s appointment, Mike Furnival, Lattice Semiconductor’s Director of Sales for Europe said: ‘This is an exciting time for Lattice as the implementation of our FPGA roadmap continues apace with the introduction of a growing portfolio of innovative FPGA products’.

‘Steve will bring both a fresh and experienced approach to the challenges that the FPGA markets presents’.

An extremely low cost programmable PCI Express solution incorporates LatticeECP and LatticeEC FPGA devices, the Genesys Logic GL9711 PCI Express PHY and Northwest Logic’s PCI Express IP core.
Available now from Lattice Semiconductor is an extremely low cost programmable PCI Express solution that incorporates the LatticeECP and LatticeEC FPGA devices, the Genesys Logic GL9711 PCI Express PHY and Northwest Logic’s PCI Express IP core. Northwest Logic, the newest member of the Lattice ispLeverCore Connection programme, provides its single lane PCI Express IP core tailored to the LatticeEC and LatticeECP device architectures. PCI Express, the next generation of PCI, uses one, two, four, eight, 16 or 32 serial signals, each operating at 2.5Gbit/s, to provide a dramatic throughput improvement over PCI.

Additionally, PCI Express software is compatible with PCI, preserving the large investments already made in PCI software.

‘PCI Express has become a standard feature in the desktop and server computers shipping today’, said Stan Kopec, Lattice Vice President of Corporate Marketing.

‘The new solution we are announcing with Genesys Logic and Northwest Logic will enable our customers to rapidly develop and field cost-effective PCI Express solutions’, Kopec concluded.

‘The combination of our PHY, the Lattice FPGA and the Northwest Logic core provides a compliant PCI Express solution that can be easily and quickly adapted by customers to meet their own unique needs’, said Miller Lin, CTO at Genesys Logic.

‘This collaboration provides customers with a solution for PCI Express applications such as networking, imaging processing, consumer electronics, test equipment and storage’.

‘This solution will be a driver of the PCI Express market, and will enable designers to upgrade their device connectivity to multi-Gigabit speed at an affordable cost’, Lin concluded.

The LatticeECP-DSP FPGA, LatticeEC FPGA, the Genesys Logic GL9711 and the Northwest Logic PCI Express IP core are available now.

The overall solution costs less than US $13.00 for volumes of 250,000 units and above.

In addition, Northwest Logic’s PCI Express development board with the above components is available now.

The base board, which includes a LatticeECP-DSP device, costs $2995 and the daughtercard with the Genesys Logic PHY costs $495.

Stratix II GX FPGAs offer a complete programmable solution for the growing number of applications and protocols requiring high-speed serial transceivers.
Altera has launched the Stratix II GX family, its third generation of FPGAs with embedded serial transceivers. Designed to deliver superior signal integrity, Stratix II GX FPGAs offer a complete programmable solution for the growing number of applications and protocols requiring high-speed serial transceivers. Stratix II GX FPGAs combine the industry’s fastest and highest-density FPGA fabric with up to 20 low-power transceivers that operate between 622Mbit/s to 6.375Gbit/s to meet the requirements of high-speed designs of today and tomorrow.

Altera carefully selected the data range of the Stratix II GX transceivers based on customer requirements and future protocol roadmaps.

The transceiver blocks provide complete support for a number of widely used protocols, including PCI Express, serial digital interface (SDI), XAUI, Sonet, Gigabit Ethernet, SerialLite II, Serial RapidIO, and Common Electrical Interface 6Gbit/s Long Reach and Short Reach (CEI-6G-LR/SR), saving valuable logic resources and simplifying protocol support.

Additionally, designers can complete their designs quickly and efficiently by using Altera’s comprehensive system solutions that include intellectual property (IP), system models, reference designs, signal integrity tools, and supporting collateral.

Stratix II GX FPGA features help designers simplify the complex task of designing systems that use high-speed protocols.

Stratix II GX FPGAs provide up to 20 full-duplex channels operating between 622Mbit/s and 6.375Gbit/s natively and down to 270Mbit/s using oversampling techniques.

Stratix II GX transceivers optimise the data eye opening using on-chip, dynamically programmable transmit pre-emphasis, receive equalisation and output voltage control.

In addition, through enhanced packaging and chip-design optimisation techniques, standard I/Os are designed to provide best-in-class signal integrity.

Stratix II GX FPGA transceivers consume only 225mW per channel at 6.375Gbit/s - less than half that of the nearest competing FPGA solution.

Stratix II GX FPGAs arrange transceivers in a quad implementation.

Each quad can be driven by two different clock sources, each with access to a high-speed and a low-speed phase-locked loop (PLL).

This combination of clocks and PLLs supports four different datarates and dramatically reduces power dissipation compared with the single PLL implementation found in competing devices.

The Stratix II GX devices’ high-density and embedded memory complement the bandwidth and performance of the device transceivers.

Built on TSMC’s industry-leading, production-qualified, 90nm process technology, the Stratix II GX family is based on the same FPGA fabric as the Stratix II FPGA family that offers unparalleled, and proven, density, performance, logic efficiency and design security.

‘Customers are already leveraging the best-in-class signal integrity of the previous Stratix GX family and the performance and density advantages of the Stratix II family’.

‘In Stratix II GX FPGAs, we’ve extended the best features from these device families to meet the needs of the marketplace over the next several years’, said Danny Biran, Vice President of Product and Corporate Marketing at Altera.

‘System engineers using Stratix II GX FPGAs, along with the complete solutions that we’ve built around them, have a highly-efficient, low-risk development path for their high-speed designs’.

‘Our collaboration with Altera in developing and correlating tools that enable modelling, design and manufacturing of robust serial interconnects has yielded excellent results’, said John D’Amborsia, Manager, Semiconductor Relations, Tyco Electronics.

‘Customers adhering to design methodology recommendations for Stratix II GX FPGAs and Tyco interconnect solutions can expect excellent signal integrity results’.

‘Our goal is to deliver complete interconnect solutions that are robust and exceed demanding requirements for performance, reliability and value’, said Tom Pitten, Vice President of Engineering and Marketing at Teradyne Connection Systems.

‘The work we have done with Altera in validating the entire interconnect continues to support this goal and provide system designers with solutions of exceptional signal integrity at leading-edge datarates’.

Engineering samples of the first member of the Stratix II GX device family will be available in Q1 2006.

Customers can start their Stratix II GX designs today using HSpice models and Altera’s Quartus II design software version 5.1.

Volume prices start at $49 for the EP2SGX30CF780 device.

Altera and Wi-LAN have formed a partnership to deliver the first programmable, low-cost WiMAX-compliant base transceiver station modem solution supporting the IEEE802.16-2004 standard.
Altera and Wi-LAN have formed a partnership to deliver the first programmable, low-cost WiMAX-compliant base transceiver station (BTS) modem solution supporting the IEEE802.16-2004 standard. The solution allows basestation developers to deliver WiMAX-compliant products that can be upgraded in the field by service providers in response to changing customer requirements and market conditions. The programmability of Altera’s FPGAs, which form an integral part of the solution, also provides developers with the flexibility to rapidly make changes to their design and still meet their time to market goals.

‘We partnered with Altera because their comprehensive product portfolio is ideal for addressing the varied needs of WiMAX applications, including performance-intensive digital signal processing, cost optimisation and high integration’, said John Seliga, Senior Vice President and General Manager of Wi-LAN’s WiMAX Semiconductor IP Solutions Division.

‘The combination of Altera’s FPGAs and embedded processors and Wi-LAN’s 802.16-2004 MAC and PHY intellectual property provides WiMAX OEMs with significant competitive advantages by minimising development time and resources, maximising first-time success and accelerating time to market’.

Designers can use either Altera’s high-density Stratix II or low-cost Cyclone II FPGAs, as well as Nios II embedded processors, with Wi-LAN’s WiMAX PHY and MAC intellectual property (IP) cores to build the BTS modem solution.

These technologies support the diverse hardware requirements, processing speeds, flexibility and integration required of the WiMAX standard.

‘With the impending commercialisation of WiMAX services, OEMs need solutions that allow them to reduce their design cycle, while service providers require the ability to easily implement and update emerging WiMAX applications’, said Arun Iyengar, Senior Director of Altera’s Wireless Business Unit.

‘Expanding Altera’s wireless ecosystem by partnering with leading IP providers such as Wi-LAN further demonstrates our commitment to enable deployment of new standards and services for the wireless market’.

Customers can purchase high-density Stratix II FPGAs, low-cost Cyclone II FPGAs and Nios II embedded processors through Altera’s worldwide distributors.

The Wi-LAN MAC and PHY IP and design documentation are available for purchase from Wi-LAN.

QuickLogic Europe has announced that the latest version of Mentor Graphics’ Precision Synthesis tool supports its ‘microwatt’ FPGAs and programmable bridges.
QuickLogic Europe has announced that the latest version of Mentor Graphics’ Precision Synthesis tool supports its ‘microwatt’ FPGAs and programmable bridges. Precision Synthesis incorporates logic synthesis algorithms optimised for minimising area and power consumption, and maximising performance for designs targeted at consumer electronics and other handheld applications. The synthesis algorithms in Precision Synthesis work to reduce the number of logic levels typically used in a design.

Reduced logic levels lead to increased performance and lower dynamic power consumption.

Using an intuitive user-interface, Precision Synthesis improves FPGA development productivity through push-button logic synthesis that improves time-to-market, and incremental and modular design flows that accelerate the number of design iterations engineers can perform per day.

The tool also provides an enhanced cross-probing feature to speed design analysis and throughput by helping designers make decisions quickly and interactively on specific design architecture improvements.

Precision Synthesis supports a broad range of industry-standard languages and offers complete support of VHDL, Verilog 2001, and SystemVerilog.

‘Mentor is a recognised technology leader in synthesis tools’, said Tom Hart, CEO of QuickLogic.

‘By extending support to our popular ‘microwatt’ FPGAs and programmable bridges, our customers now have access to world-class synthesis tools that can significantly improve the performance, utilisation and power consumption of their designs’.

‘Dedicated Precision Synthesis users, whose systems require the lowest power FPGA available, now have native tool chain support for QuickLogic devices that fulfil this need’.

‘Mentor Graphics is pleased to support QuickLogic to ensure that the powerful push-button and interactive optimisation capabilities in our Precision Synthesis tool complement the full range of innovative features available in QuickLogic’s new device families’, said Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics.

‘We believe our advanced synthesis support enables a very practical solution for the many companies competing in the consumer electronics arena, especially in handheld designs that demand efficient use of both power and area’.

QuickLogic device support is available in Precision Synthesis from Mentor Graphics as an overlay kit.

Lattice Semiconductor has introduced its second generation Power Manager II devices, along with details of the first device available, the ispPAC-POWR1220AT8.
Lattice Semiconductor has introduced its second generation Power Manager II devices, along with details of the first device available, the ispPAC-POWR1220AT8. The Power Manager II family is a functional superset of Lattice’s earlier award winning ispPAC power manager mixed-signal devices that provide a complete power management solution for printed circuit boards (PCBs) through an optimised set of programmable digital and analogue functions. All power manager devices provide a standard, off-the-shelf programmable mixed-signal solution for power management that enhances reliability and speeds time-to-market.

Analogue features such as input comparator thresholds and digital functions such as supply control sequences are programmed into non-volatile E2CMOS elements on the devices using an IEEE1149.1 protocol.

The new Power Manager II devices add power supply margining and trimming to first generation device features such as power supply voltage sequencing and monitoring.

‘Our power manager devices were introduced in 2003′, said Stan Kopec, Lattice Vice President of Corporate Marketing.

‘Since then, Lattice has led the industry in applying programmability to mixed-signal power management ICs’.

‘Now our second generation Power Manager II devices, in addition to integrating all power supply management functions into one chip, provide more precise monitoring and more accurate voltage control, and that improves system reliability’.

‘The Power Manager II devices are ideal power management solutions for emerging applications and specifications, such as AdvancedTCA (Advanced Telecom Computing Architecture)’.

‘For example, the1220AT8 device can act as a coprocessor to an Intelligent Platform Management Controller (IPMC) in an AdvancedTCA Field Replaceable Unit (FRU)’.

‘The sequence control intelligence built into the on-chip CPLD can interrupt the processor under fault conditions, reducing the processing load on the IPMC’.

The POWR1220AT8 device integrates a 48 Macrocell ruggedised CPLD, dual precision voltage monitoring comparators with an accuracy of 0.5%, a 10bit analogue-to-digital convertor (ADC) for voltage measurements, and eight 8bit digital-to-analogue convertors (DAC) for trimming power supplies.

The integrated I2C interface enables a microcontroller, such as an IPMC, to read the status of all the comparators (inputs and outputs) as well as control the power supply voltage level across its entire operating range.

Additionally, the controller can measure not only locally generated voltages, but current levels as well.

The ispPAC POWR1220AT8 device integrates a unique Margin and Trim Block (MTB) that provides a flexible mechanism for both setting and maintaining the output voltage of a power supply to within 1% of its set value (’trimming’), as well as the ability to vary a power supply voltage to +/-5% of its target value for quality control purposes (’margining’).

The MTB consists of 8 TrimCells that simultaneously control the power supply voltages of up to eight supplies.

Each TrimCell has an 8bit DAC and 6 DAC registers for margining and trimming flexibility.

Accuracy of the trimmed voltage across operating temperature, load and age of the power supply is achieved through a digital closed loop trim control circuit.

This control circuit continuously compares the voltage set point for a given power supply with the output of the on-chip ADC monitoring that power supply voltage.

The resulting error signal automatically increases or decreases the DAC voltage, maintaining the power supply voltage at a constant value.

Furthermore, the external microcontroller can monitor the power supply voltage through the on-chip ADC and directly control the corresponding DAC through the I2C interface.

In addition, the TrimCell also can store four different DAC code settings or configurations that can easily be selected using hardware pins dedicated to voltage profile selection.

Designs for the ispPAC-POWR1220AT8 device are implemented using Lattice’s Windows-based PAC-Designer Software version 4.0.

The embedded LogiBuilder software module in PAC-Designer supports the implementation of multiple control sequence algorithms: for example, IPMC command response, Payload power management and AMC management required in ATCA applications.

Designers are able to implement complex algorithms using seven types of instructions.

With an extremely intuitive design flow, users can learn its operation and complete designs in minutes.

Further enhancing its ease-of-use, the Margin and Trim macro embedded in PAC-Designer 4.0 automatically determines the resistor network for a given power supply based on its output voltage required.

The PAC-Designer 4.0 software is available for download free of charge from the Lattice web site.

High volume (10KU+) pricing for the ispPAC-POWR1220AT8 devices in the 100-pin TQFP package and industrial temperature range is $5.50.

Samples are available now.