Texas Instruments and Xilinx have developed an FPGA-based deserialiser reference design that deserialises bitstreams from TIs ADS527x ADC family.
Texas Instruments and Xilinx have developed an FPGA-based deserialiser reference design. This new reference design, which deserialises bitstreams from TIs ADS527x ADC family, and accompanying application note provide a quick and easy solution for designers to integrate a serial, high-speed LVDS receiver into the Xilinx Virtex-II series, Virtex-II Pro and Spartan-3 FPGAs. Systems designers can now effectively leverage the serial-to-parallel processing capabilities and software programmability of FPGAs to accelerate operations for specialised, high-performance processing functions.

The ability to achieve much higher levels of overall system performance is especially important for multi-channel applications such as ultrasound, instrumentation and wireless communications.

The deserialiser reference design accepts up to eight channels simultaneously and provides automatic deskew and clock alignment functions.

Each ADC output is serialised and transmitted through a separate LVDS serial pair.

An independent frame clock and serial data clock are provided to allow for easy deserialisation.

The Xilinx reference design provides the necessary timing to accept these extremely fast input signals and translate them into commonly used parallel output busses.

The serial LVDS interface format provides several distinct advantages to the system manufacturer.

Lower pin count, both on the ADC and the FPGA, means less routing lines and lower cost boards.

The LVDS interface itself is a differential current mode interface that provides both immunity to external noise and extremely low crosstalk injection of noise into the printed circuit board.

These advantages translate to lower cost and higher system reliability.