Software automates standard cell design optimisation for timing, area and leakage power, accelerating design closure for high-speed standard cell designs.
Zenasis Technologies has expanded its series of ZenTime products: ZenTime-GT, ZenTime-AT and ZenTime-PT automate standard cell design optimisation for timing, area and leakage power, respectively, accelerating design closure for high-speed standard cell designs. Timing closure continues to be a challenge with high performance standard cell designs; leakage power is increasing exponentially in nanometre designs and can no longer be ignored. IP core integration and migration further complicate the process.

The limitations of traditional approaches result in multiple, lengthy design iterations and a substantial amount of manual intervention.

By using patented ‘hybrid optimisation’ technology to analyse and optimise standard cell designs at the logical, physical, and transistor levels, Zenasis’ ZenTime optimisation products achieve many of the benefits of custom design in a manner transparent to the designer.

‘There are counterbalancing forces that must be managed with high-speed nanometre designs’, said Dennis Harmon, Zenasis’ CEO and President.

‘Our ZenTime products automatically resolve designers’ conflicting optimisation goals within project deadlines, and allow them to push their quality of results to the design limit while reducing product costs’.

The new ZenTime products bring significant new capabilities to designers employing standard cell libraries as part of their design methodology.

With ZenTime-GT, designers can achieve performance improvements without changing their existing process technologies to smaller, lower yield geometries.

ZenTime-GT employs multiple timing optimisation techniques including: buffer insertion, such as buffer tree construction and restructuring; gate sizing for discrete drive strengths; pin permutation; use of inverted logic gates; and output stage sizing.

ZenTime-GT is tightly integrated with placement and static timing analysis engines and can be plugged directly into existing standard cell design flows.

ZenTime-AT works in conjunction with ZenTime-GT to manage the area tradeoffs that can be associated with meeting timing constraints.

Following timing optimisation with ZenTime-GT, ZenTime-AT recovers area impacted by timing optimisation as well as from positive slack points.

This area optimisation steps allow designers to control their product cost.

ZenTime-PT works in conjunction with ZenTime-GT to improve the leakage power trade-offs that can be associated with meeting timing constraints.

Following timing optimisation with ZenTime-GT, ZenTime-PT reduces the leakage power on the noncritical paths.

The power optimisation step enables efficient use of low-Vt cells in a multi-Vt design, resulting in longer battery life.

ZenTime-GT.

ZenTime-AT and ZenTime-PT are tightly integrated into existing standard-cell design flows; they are typically used following the logic and physical synthesis stage.

The input to ZenTime products is a Verilog netlist, DEF and SDC files, and library information such as GDSII, LIB, LEF, Verilog and Spice netlists.

ZenTime products output an optimised Verilog netlist and DEF, plus GDSII, LIB, LEF, Verilog and Spice netlists for the cells created on-the-fly.

The ZenTime family of products now includes ZenTime-GT, ZenTime-AT, ZenTime-PT and ZenTime-XT (formerly ZenTime).

ZenTime-XT focuses on optimisation at the transistor level, works iteratively with gate level technology to find and fix timing bottlenecks, and interfaces to existing standard cell library view creation flows.

ZenTime-GT, ZenTime-AT, ZenTime-PT and ZenTime-XT production versions are available immediately with flexible package pricing.

ZenTime’s product family runs on Linux and Sun-Solaris platforms.