Lattice Semiconductor has introduced its second generation Power Manager II devices, along with details of the first device available, the ispPAC-POWR1220AT8.
Lattice Semiconductor has introduced its second generation Power Manager II devices, along with details of the first device available, the ispPAC-POWR1220AT8. The Power Manager II family is a functional superset of Lattice’s earlier award winning ispPAC power manager mixed-signal devices that provide a complete power management solution for printed circuit boards (PCBs) through an optimised set of programmable digital and analogue functions. All power manager devices provide a standard, off-the-shelf programmable mixed-signal solution for power management that enhances reliability and speeds time-to-market.

Analogue features such as input comparator thresholds and digital functions such as supply control sequences are programmed into non-volatile E2CMOS elements on the devices using an IEEE1149.1 protocol.

The new Power Manager II devices add power supply margining and trimming to first generation device features such as power supply voltage sequencing and monitoring.

‘Our power manager devices were introduced in 2003′, said Stan Kopec, Lattice Vice President of Corporate Marketing.

‘Since then, Lattice has led the industry in applying programmability to mixed-signal power management ICs’.

‘Now our second generation Power Manager II devices, in addition to integrating all power supply management functions into one chip, provide more precise monitoring and more accurate voltage control, and that improves system reliability’.

‘The Power Manager II devices are ideal power management solutions for emerging applications and specifications, such as AdvancedTCA (Advanced Telecom Computing Architecture)’.

‘For example, the1220AT8 device can act as a coprocessor to an Intelligent Platform Management Controller (IPMC) in an AdvancedTCA Field Replaceable Unit (FRU)’.

‘The sequence control intelligence built into the on-chip CPLD can interrupt the processor under fault conditions, reducing the processing load on the IPMC’.

The POWR1220AT8 device integrates a 48 Macrocell ruggedised CPLD, dual precision voltage monitoring comparators with an accuracy of 0.5%, a 10bit analogue-to-digital convertor (ADC) for voltage measurements, and eight 8bit digital-to-analogue convertors (DAC) for trimming power supplies.

The integrated I2C interface enables a microcontroller, such as an IPMC, to read the status of all the comparators (inputs and outputs) as well as control the power supply voltage level across its entire operating range.

Additionally, the controller can measure not only locally generated voltages, but current levels as well.

The ispPAC POWR1220AT8 device integrates a unique Margin and Trim Block (MTB) that provides a flexible mechanism for both setting and maintaining the output voltage of a power supply to within 1% of its set value (’trimming’), as well as the ability to vary a power supply voltage to +/-5% of its target value for quality control purposes (’margining’).

The MTB consists of 8 TrimCells that simultaneously control the power supply voltages of up to eight supplies.

Each TrimCell has an 8bit DAC and 6 DAC registers for margining and trimming flexibility.

Accuracy of the trimmed voltage across operating temperature, load and age of the power supply is achieved through a digital closed loop trim control circuit.

This control circuit continuously compares the voltage set point for a given power supply with the output of the on-chip ADC monitoring that power supply voltage.

The resulting error signal automatically increases or decreases the DAC voltage, maintaining the power supply voltage at a constant value.

Furthermore, the external microcontroller can monitor the power supply voltage through the on-chip ADC and directly control the corresponding DAC through the I2C interface.

In addition, the TrimCell also can store four different DAC code settings or configurations that can easily be selected using hardware pins dedicated to voltage profile selection.

Designs for the ispPAC-POWR1220AT8 device are implemented using Lattice’s Windows-based PAC-Designer Software version 4.0.

The embedded LogiBuilder software module in PAC-Designer supports the implementation of multiple control sequence algorithms: for example, IPMC command response, Payload power management and AMC management required in ATCA applications.

Designers are able to implement complex algorithms using seven types of instructions.

With an extremely intuitive design flow, users can learn its operation and complete designs in minutes.

Further enhancing its ease-of-use, the Margin and Trim macro embedded in PAC-Designer 4.0 automatically determines the resistor network for a given power supply based on its output voltage required.

The PAC-Designer 4.0 software is available for download free of charge from the Lattice web site.

High volume (10KU+) pricing for the ispPAC-POWR1220AT8 devices in the 100-pin TQFP package and industrial temperature range is $5.50.

Samples are available now.