ST Assembly Test Services (STATS) has launched a new integrated circuit package for the wired and wireless communications markets.
ST Assembly Test Services (STATS) has launched a new integrated circuit package for the wired and wireless communications markets. The new Stacked Die Ball Grid Array (SDBGA) is distinguished by its stacking feature, combining various ICs in one package, which can significantly reduce not only manufacturing cost but also reduce testing time and real estate on the motherboard. Both the mounting area and chip weight of an SDBGA can be reduced as much as 70%, compared with conventional packages.

“The SDBGA’s multi-die application easily meets current market demand for communications devices.

Increasingly, these devices pack a lot of capability into a smaller size, cost less, are easier to produce and offer faster time to market than a single chip solution”, says BJ Han, STATS Chief Technology Officer.

SDBGA has all the characteristics of near Chip Scale Packages (CSPs) - advanced packages that are lighter in weight, a smaller size and provide higher performance.

It is the latest addition to STATS’ CSP family following the introduction of the Flip Chip Small-Thin Plastic BGA (FCstPBGA) last August.

Wireless communications is a key application.

Handphones, for example, contain both flash and SRAM ICs and by stacking these on top of one another in an SDBGA package, the chip size is retained with enhanced capability.

The SDBGA offers an ideal configuration for the emerging memory and logic combination in one package.

Memory density and electrical performance are improved while reducing the package and testing costs that can occur prior to installation into a product.

Other applications for Stacked Die BGAs include MP3, MD players, and handheld devices such as PDAs, camcorders and palmtops.

With its two-in-one feature, the total SDBGA package height is typically 1.4mm.

Popular SDBGA sizes range from 8 x 8 to 14 x 14mm, with pin counts between 80 and 140.