The feature-rich ZL30116 and ZL30119 phase locked loops are the lowest jitter and smallest devices for managing Sonet/SDH Stratum 3 synchronisation at OC-48/STM-16 rates.
Zarlink Semiconductor has introduced the industry’s first single-chip ultra-low-jitter synchronisers for Sonet/SDH multiservice applications. The feature-rich ZL30116 and ZL30119 PLLs (phase locked loops) are the lowest jitter and smallest devices for managing Sonet/SDH Stratum 3 synchronisation at OC-48/STM-16 rates. With the explosive growth of Ethernet and other packet-based traffic, carriers must protect their investments in Sonet/SDH infrastructure while accommodating multiple traffic types.

Network equipment vendors are developing Sonet/SDH multiservice products, including MSPPs (multiservice provisioning platforms) and MSSPs (multiservice switching platforms) that allow carriers to mix voice and packet services by only replacing edge network elements.

Industry research values this market at US $3.5 billion in 2005 with equipment installations predicted to grow 26% in 2006.

In turn, semiconductor companies are delivering next-generation ADMs (add-drop multiplexers), which are small, high-performance system-on-chip devices that process packetised traffic more efficiently.

ADMs require multiple clocks to deal with multiple traffic types and only Zarlink’s new timing chips offer ADM designers a comprehensive set of Stratum 3 clock synthesis capabilities while meeting OC-48/STM-16 performance requirements.

Leading network equipment vendors are currently evaluating Zarlink’s new PLLs for their next-generation designs.

The highly programmable ZL30116 and ZL30119 chips generate three independent clock families, eliminating the need for external dividers or clock-multiplying PLLs.

The devices match the reference frequency requirements of any commercial Sonet/SDH PHY (physical interface), and deliver the industry’s widest range of selectable output frequencies for low-jitter clocks: 19.44, 38.88, 51.84, 77.76, 311.04 and 622.08MHz.

The ZL30116 device implements the market’s most extensive suite of master/slave clock redundancy capabilities.

This chip is the only synchroniser to embed zero delay PLL capabilities that compensate for external clock propagation delays to meet the stringent phase alignment requirements of AdvancedTCA clock buses.

Digital PLL-based synchronisers are used in Sonet/SDH equipment to manage numerous clocks within a multiservice switching environment.

However, most digital PLLs generate too much jitter for interfaces at rates above OC-3, necessitating a separate analogue PLL to ‘clean up’ the noise.

Multichip combinations or modules may be as large as one square inch.

Zarlink is first to deliver a single-chip synchroniser capable of generating less than 1ps of jitter.

The ZL30116 Stratum 3 system synchroniser and ZL30119 line card synchroniser are pin-compatible and measure just 9 x 9mm.

The ZL30116 and ZL30119 devices provide superior network synchronisation features including holdover and hitless reference switching.

The chips ensure continued operation during network disruptions or upgrades by monitoring the input reference clocks and providing hitless reference switching on detecting a bad or failed reference clock.

The PLLs maintain stable and reliable output clocks in the presence of network or intra-system jitter and wander conditions.

If the source of network synchronisation is temporarily lost, the devices automatically switch into holdover mode and continue to generate output clocks based on data collected from past reference signals.

The ZL30116 and ZL30119 PLLs are available now.