A research team led by Jakub Kedzierski at the University of California at Berkeley has developed a transistor with a 15nm (0.015 micro m) gate using electron beam lithography.
One of the major problems with thin silicon-on-insulator systems is the large series resistance of the insulator layer. The team used two low barrier silicide source/drains in a 100nm layer that was thinned to 14nm to get round the problem.
As the silicide source/drain switches on, it passes through the source body flat band condition and so the body of the silicon blocks the current flow. Above this condition, the Schottky barrier is the dominant current barrier.